Hi All,
I am really hoping someone will be kind enough to shed some light on the following.
I don't have much experience with amplifiers and am struggling to get my head around a specific aspect of the data sheet for the PAM8109 chip
https://www.diodes.com/assets/Datasheets/PAM8019.pdf
Pin 4 in the datasheet is labelled as "4 -- Bypass -- Bias Voltage for Power Amplifier"
My 5V audio source is already biased to 2.5V.
My question is:
1. Does this chip accept a signal that has already been biased.
2. What is the chip asking me to supply on pin #4
3. The example application seems to imply that its 0V connected to ground via the bypass capacitor.
Am i good to go ahead and feed in my existing signal, and the bypass pin would only be fed a voltage if the signal was not biased and then would handle the bias internally if a reference voltage was applied to that pin.
I feel like i'm making too many assumptions and just guessing at this point.
Thanks in advance and apologies if i am misunderstanding to the point my question makes no actual sense
I am really hoping someone will be kind enough to shed some light on the following.
I don't have much experience with amplifiers and am struggling to get my head around a specific aspect of the data sheet for the PAM8109 chip
https://www.diodes.com/assets/Datasheets/PAM8019.pdf
Pin 4 in the datasheet is labelled as "4 -- Bypass -- Bias Voltage for Power Amplifier"
My 5V audio source is already biased to 2.5V.
My question is:
1. Does this chip accept a signal that has already been biased.
2. What is the chip asking me to supply on pin #4
3. The example application seems to imply that its 0V connected to ground via the bypass capacitor.
Am i good to go ahead and feed in my existing signal, and the bypass pin would only be fed a voltage if the signal was not biased and then would handle the bias internally if a reference voltage was applied to that pin.
I feel like i'm making too many assumptions and just guessing at this point.
Thanks in advance and apologies if i am misunderstanding to the point my question makes no actual sense
The circuit shown will just work.
1) Its inputs are AC coupled with 1µF caps so no issue for your source (or any source really).
2) Pin 4 is the bypass (i.e. decoupling) connection for the internal bias network - use a capacitor to ground just as shown.
3) This pin definitely isn't at 0V, don't mess with it or you could muck up the internal biasing. The cap to ground is to suppress noise and provide low impedance, and to smoothly powerup and powerdown, if the technology existed to put a 2.2µF capacitor on the chip this pin would be unnecessary, but on-chip caps are nothing like that value so the cap has to be external to the chip.
I think you are confusing input offset DC voltage (which it will have, but which is finessed by capacitive coupling) with an internal bias network. Their diagram is confusing as the bypass pin will go to the "bias and Vref" section, not just the control logic...
1) Its inputs are AC coupled with 1µF caps so no issue for your source (or any source really).
2) Pin 4 is the bypass (i.e. decoupling) connection for the internal bias network - use a capacitor to ground just as shown.
3) This pin definitely isn't at 0V, don't mess with it or you could muck up the internal biasing. The cap to ground is to suppress noise and provide low impedance, and to smoothly powerup and powerdown, if the technology existed to put a 2.2µF capacitor on the chip this pin would be unnecessary, but on-chip caps are nothing like that value so the cap has to be external to the chip.
I think you are confusing input offset DC voltage (which it will have, but which is finessed by capacitive coupling) with an internal bias network. Their diagram is confusing as the bypass pin will go to the "bias and Vref" section, not just the control logic...
Thankyou for the reply:
I mistated you are correct, My source provides the signal with a 2.5V DC offset.
"Its inputs are AC coupled with 1µF caps so no issue for your source (or any source really)."
Ah yes, the 1uF caps are basically removing the DC offset and giving the amp just the audio with no DC offset.
"Pin 4 is the bypass (i.e. decoupling) connection for the internal bias network - use a capacitor to ground just as shown."
Ah, thei cricuit diagram confused me as its attached at the bottom of a voltage dividor in their schematic which has nothing to do with this capacitor, just happened to be the sharing the same ground in the diagram.
So all i need is as below.
"This pin definitely isn't at 0V, don't mess with it or you could muck up the internal biasing. The cap to ground is to suppress noise and provide low impedance, and to smoothly powerup and powerdown, if the technology existed to put a 2.2µF capacitor on the chip this pin would be unnecessary, but on-chip caps are nothing like that value so the cap has to be external to the chip"
Thankyou, yup all makes sense now.
"I think you are confusing input offset DC voltage (which it will have, but which is finessed by capacitive coupling) with an internal bias network. Their diagram is confusing as the bypass pin will go to the "bias and Vref" section, not just the control logic..."
Yeah the schamitic they have tripped me up a bit there.
THankyou for your help.
I mistated you are correct, My source provides the signal with a 2.5V DC offset.
"Its inputs are AC coupled with 1µF caps so no issue for your source (or any source really)."
Ah yes, the 1uF caps are basically removing the DC offset and giving the amp just the audio with no DC offset.
"Pin 4 is the bypass (i.e. decoupling) connection for the internal bias network - use a capacitor to ground just as shown."
Ah, thei cricuit diagram confused me as its attached at the bottom of a voltage dividor in their schematic which has nothing to do with this capacitor, just happened to be the sharing the same ground in the diagram.
So all i need is as below.
"This pin definitely isn't at 0V, don't mess with it or you could muck up the internal biasing. The cap to ground is to suppress noise and provide low impedance, and to smoothly powerup and powerdown, if the technology existed to put a 2.2µF capacitor on the chip this pin would be unnecessary, but on-chip caps are nothing like that value so the cap has to be external to the chip"
Thankyou, yup all makes sense now.
"I think you are confusing input offset DC voltage (which it will have, but which is finessed by capacitive coupling) with an internal bias network. Their diagram is confusing as the bypass pin will go to the "bias and Vref" section, not just the control logic..."
Yeah the schamitic they have tripped me up a bit there.
THankyou for your help.