Grounding unused inputs

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A quick look at the input topology should clue you in.

CMOS uses a complementary pair of common-source MOSFETs. The gates are connected together, and the sources are tied to the supply rails. There are no pulldowns or low impedance paths from the gates to the rails, only the ESD protection diodes, which are reverse biased when the gates are between the rails.

The MOSFETs have a threshold voltage that varies with the process and the intended supply voltage, but in all cases the threshold is well below the minimum supply voltage. With me so far?

If the gates happen to "float" to a voltage halfway between the rails, you could have both the FETs turned on hard at the same time. This is Not A Good Thing for a number of reasons, not least of which is that it can destroy the device!

Unterminated gates are also susceptible to RFI and other forms of signal leakage. If you have the gates transitioning through the device's active range, you can induce all sorts of lovely hash into the supply rails.

TTL, OTOH, has what is effectively a common-base input topology. The input is the emitter of an NPN transistor whose base voltage is well defined, so leaving an input disconnected just makes the TTL gate think it has a high logic level input.

It's generally considered good practice to pull an unused TTL input up to +5V through a resistor, but it isn't going to hurt anything to let it float.
 
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