I'm trying to simulate this very interesting circuit by Graham Maynard. Essentially a discrete op amp with Class A output stage.
It's oscillating pretty nastily in LTSpice. I've tried higher values for the feedback cap and lower values for the feedback resistor (lower gain), and it just gets worse. With even 27pf in the feedback loop, it simply doesn't work at all - only oscillation.
Any thoughts on why it's not working? Maybe it needs some sort of internal compensation?
It's oscillating pretty nastily in LTSpice. I've tried higher values for the feedback cap and lower values for the feedback resistor (lower gain), and it just gets worse. With even 27pf in the feedback loop, it simply doesn't work at all - only oscillation.
Any thoughts on why it's not working? Maybe it needs some sort of internal compensation?
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You haven't made one then, just playing with approximations.
It may well work in practice. Tried replacing the 100R NFB shunt with 470R or 1k ... that might stop the NFB from turning into PFB.
Would I make one ... no. It is far too complicated when there are dedicated ultra low noise, utra stable ICs available.
It may well work in practice. Tried replacing the 100R NFB shunt with 470R or 1k ... that might stop the NFB from turning into PFB.
Would I make one ... no. It is far too complicated when there are dedicated ultra low noise, utra stable ICs available.
R7/R6 implies a closed loop amplification of 1000x (60dB), but even with Q1/Q2 transconductance boosters I doubt if there is enough open loop gain.
The R6/C1 combo is not really preferred: a 2200uF nonpol cap?
The R7/C3 hpf is set just under 1MHz, but stray capacitance will lower that further.
A full band open loop Bode plot will reveal its performance better.
The R6/C1 combo is not really preferred: a 2200uF nonpol cap?
The R7/C3 hpf is set just under 1MHz, but stray capacitance will lower that further.
A full band open loop Bode plot will reveal its performance better.
IIUC, Graham (RIP) was very focused on ‘first cycle distortion’ so tried to avoid or minimise phase lag compensation.
Looking at the circuit, you should easily be able to stabilise it with a small cap (22pF to 100pF) across the base emitter junction of Q7. I would omit C3 until you got the overall circuit stable. C3 can help claw back a bit of phase margin, but I’ve found in practice it’s usually not needed.
The gain is very high - is that correct?
Best way to proceed with this is to do some loop gain plots and look at phase and gain margin and then adjust the comp cap for the best result (close to 90 degrees and >10 dB gain margin should be easily achievable).
🙂
Looking at the circuit, you should easily be able to stabilise it with a small cap (22pF to 100pF) across the base emitter junction of Q7. I would omit C3 until you got the overall circuit stable. C3 can help claw back a bit of phase margin, but I’ve found in practice it’s usually not needed.
The gain is very high - is that correct?
Best way to proceed with this is to do some loop gain plots and look at phase and gain margin and then adjust the comp cap for the best result (close to 90 degrees and >10 dB gain margin should be easily achievable).
🙂
So, an update on this.
Playing around with the circuit, the whole thing would oscillate with any gains lower than 60db (100k R7, 100R R6).
Adding up to 200p across Q7 didn't seem to help, nor did adding emitter degeneration in Q3/Q4/Q7.
I managed to get it stable by taking a cue from the 2520 DOA and putting an RC shunt of 1000p and 100R across the collectors of the LTP (Q3 and Q4). I also added 33p across Q7. This seems to give it a nice phase margin all the way down to a gain of 2.
Using 0.01u in the shunt and 100p across Q7 makes it unity gain stable.
Both of these remedies also reduce the bandwidth at higher gains (starts to roll off around 20k at 60db of gain), so it seems like the compensation should be optimized for the application.
I didn't change anything except the value of C3, that's what I found so strange. I don't understand the offset problem at all - it did this with any values of C3 over about 20pf. Maybe the oscillation is making the whole circuit latch up?
Playing around with the circuit, the whole thing would oscillate with any gains lower than 60db (100k R7, 100R R6).
Adding up to 200p across Q7 didn't seem to help, nor did adding emitter degeneration in Q3/Q4/Q7.
I managed to get it stable by taking a cue from the 2520 DOA and putting an RC shunt of 1000p and 100R across the collectors of the LTP (Q3 and Q4). I also added 33p across Q7. This seems to give it a nice phase margin all the way down to a gain of 2.
Using 0.01u in the shunt and 100p across Q7 makes it unity gain stable.
Both of these remedies also reduce the bandwidth at higher gains (starts to roll off around 20k at 60db of gain), so it seems like the compensation should be optimized for the application.
I didn't change anything except the value of C3, that's what I found so strange. I don't understand the offset problem at all - it did this with any values of C3 over about 20pf. Maybe the oscillation is making the whole circuit latch up?
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