First one (follower style) are better because of the low transconductance of the laterals.
It's anyway better drive gates from the low-impedance previous follower output rather than raltively highish common emitter load.
But, being really, use faster trannies, provide first follower temperature stabilisation and use common base last VAS stage.
So, sometning like attached will be better.
It's anyway better drive gates from the low-impedance previous follower output rather than raltively highish common emitter load.
But, being really, use faster trannies, provide first follower temperature stabilisation and use common base last VAS stage.
So, sometning like attached will be better.
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one vote each.
i like cct1 for less parts, but Q7/8 need heatsinking.
what would be a good method to evaluate these circuits?
i like cct1 for less parts, but Q7/8 need heatsinking.
what would be a good method to evaluate these circuits?
The second option is pretty much identical to my own design here:
My MOSFET amplifier designed for music.
and it has proved worthy on all counts. Lateral FET's are a generally easy load to drive.
My MOSFET amplifier designed for music.
and it has proved worthy on all counts. Lateral FET's are a generally easy load to drive.
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For ultimate bandwidth far beyond audibility posting #2 is the way to go. Requires gate resistors anyway. The rising impedance even of fast emitter followers is the limiting factor. I got best results with medium-power lat-FET source-followers - obsolete for decades now.
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I'd strongly suggest never omitting protection zeners on any MOSFET driver circuit, mounted directly on the device source/gate terminals if possible. Back-to-back zeners
may be needed depending on topology.
may be needed depending on topology.
I would simply use one of these :
https://www.analog.com/media/en/technical-documentation/data-sheets/6090fe.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/6090fe.pdf
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I am using LTC6090-5 in my design, but I am using 8 Exicon mosfets per channel and a few other notable changes.
I would use LED ' s in place of the 6.8 k resistors
to preclude xover with transient power supply sag .
to preclude xover with transient power supply sag .
The problem with #2 is that 1.5K is very slow to pull the gate capacitance off. It may be "fast enough" depending on the capacitance of the FETs you are using. You can improve #2 by replacing the 1.5K resistors with a smaller resistor and/or an active pull-off circuit. It is common to see a small resistor in series with forward diodes or some other source of a sub- vto voltage. You can also cross couple the two gates with a capacitor so that the opposite driver drives one FET on while it drives the opposite FET off. The problem is that cross-coupling a CFP results in poor PSRR. Failure to drive outputs off kills BJT amps when they are driven at 10KHz+ at power because it results in a shoot through current across both devices. This could also happen to FETs here where the 1.5K fails to drain the gate before the next on cycle.
A couple other things:
1. The CFP output is not as stable as the follower output, more susceptible to capacitive loading. Normally this is a trade-off in order to achieve gain in the OP but this circuit has no such gain. Gain in the OP means that the voltage swing is not limited by the VAS.
2. The VAS bias follows from the IPS and is sensitive to the rail voltage. The result will be that the cross-over bias will be unpredictable and unstable. I suggest regulating the voltage on the 1000uF caps (C3,C4) with forward diodes.
1. The CFP output is not as stable as the follower output, more susceptible to capacitive loading. Normally this is a trade-off in order to achieve gain in the OP but this circuit has no such gain. Gain in the OP means that the voltage swing is not limited by the VAS.
2. The VAS bias follows from the IPS and is sensitive to the rail voltage. The result will be that the cross-over bias will be unpredictable and unstable. I suggest regulating the voltage on the 1000uF caps (C3,C4) with forward diodes.
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1 vote for the 1st solution. It is quite fast drive for the MOSFETs. The only note, that I would use some faster BJTs as driver, such as KSC3503/KSA1381. Another note is the missing thermal compensation for the drivers.
Sajti
Sajti
Reading the suggestions, you have every reason in the world to be confused and to make a haphazard decision. Theoretical study and experience are now obsolete assessment methods and replaced with deceptive circuit simulation. Version #2 is the way to go.
Note that diodes or VBE multipliers on the 1000uF caps would create a useful thermal compensation, as well as remove the supply voltage sensitivity. Alternately, R11 and R12 could be replaced with current sources. And, of course you could put diodes in series with R7 and R8, or R10 (and reduce the resistors).
In either case you should fine tune the thermal sensitivity for as close to zero thermal constant as possible. As you probably know, You can step the simulation temperature in LTSpice.
In either case you should fine tune the thermal sensitivity for as close to zero thermal constant as possible. As you probably know, You can step the simulation temperature in LTSpice.
although not shown in the circuits i posted, i will be running the input/vas/(driver) from regulated rails, so i assume this will cover the items mentioned in post 17.
I suspect circuit 1 would result in better stability margins and greater consistency of distortion with frequency. The high input capacitance of the FETs will diminish gain of drivers at high frequency in circuit 2. Testing beyond audio bandwidth, and seeing how the distortion grows is a reflection of how well feedback behaves when a design is under stress. Current through the FET affects gate conditions.
For circuit 1 the compensation capacitors can be driven from the driver. Since this has no gain and can supply current, HF distortion will improve. Stability might reduce marginally but should still be better than circuit 2.
Circuit 1 drivers seem to have excessive current even though rails values are not published. Laterals don't really need thermal compensation so adjusting the bias of the drivers to reasonable values would enable the emitter resistor to provide thermal compensation. Zener protection for FET gates is recommended.
For circuit 1 the compensation capacitors can be driven from the driver. Since this has no gain and can supply current, HF distortion will improve. Stability might reduce marginally but should still be better than circuit 2.
Circuit 1 drivers seem to have excessive current even though rails values are not published. Laterals don't really need thermal compensation so adjusting the bias of the drivers to reasonable values would enable the emitter resistor to provide thermal compensation. Zener protection for FET gates is recommended.
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analog_sa, how are you doing? The voltage follower constitutes a feeble driver for output transistors.
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This topology should be stable without any phase compensation capacitor. Zener diodes are far too slow and provide no protection against transient voltages. The lateral FETs have internal protection diodes.
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This topology should be stable without any phase compensation capacitor. Zener diodes are far too slow and provide no protection against transient voltages. The lateral FETs have internal protection diodes.