Diy professional DAC & questions on word clock
Hi everybody 🙂
I'm a student in sound engineering, and prior was a student in electronics and industrial IT.
I plan to design a full digital audio system, from ADC to DAC. But I still lack knowledge, and I have some questions to ask to you.
My goal is to make a professional system, not an audiophile system.
So here we start!
One of the main problems with digital audio is the jitter of the clock. A DAC could be designed to try to solve this problem, using the well-known topology:
In->Receiver->ASRC->oversampling->FIR ->DAC->IV->analog filter -> out
This is quite complex because we try to cancel the jitter. We have to build a good quality clock inside each element we will use (ie inside the DAC, ADC, and interface). And ASRC is not a "magical chip".
My idea is that we are in the professinal field. So why not buy a good quality word clock and stop using seperate clocks? This is probably the way to the lowest jitter, and keeping prices down - a clock in each element is expensive, if we don't need them, just don't buy them....
I read many topics on transport, I think I'll go with Toslink as jitter on optical links are the easiest to get rid of.
The topology should then be:
In->Receiver->oversampling->FIR->DAC->IV->filter->out.
Then it becomes harder!
Let's use a PLL on the receiver, as I don't want it to add it's own jitter: it should then clock data out at the same rate as the data comes in. I fear of clocking it directly with the word clock, but maybe I'm wrong?
Let's clock the Oversampling and the DAC to the word clock.
What is exactly the frequency given by the word clock? Because it's not the word clock that I need now - it's the bit clock, that depends on the resolution and the oversampling (and of course the sample rate).
How to get this bit clock?
Let's start with these questions, when I'll have solved them I'll go to the next ones 😛
Thank you very much,
Nicolas
Hi everybody 🙂
I'm a student in sound engineering, and prior was a student in electronics and industrial IT.
I plan to design a full digital audio system, from ADC to DAC. But I still lack knowledge, and I have some questions to ask to you.
My goal is to make a professional system, not an audiophile system.
So here we start!
One of the main problems with digital audio is the jitter of the clock. A DAC could be designed to try to solve this problem, using the well-known topology:
In->Receiver->ASRC->oversampling->FIR ->DAC->IV->analog filter -> out
This is quite complex because we try to cancel the jitter. We have to build a good quality clock inside each element we will use (ie inside the DAC, ADC, and interface). And ASRC is not a "magical chip".
My idea is that we are in the professinal field. So why not buy a good quality word clock and stop using seperate clocks? This is probably the way to the lowest jitter, and keeping prices down - a clock in each element is expensive, if we don't need them, just don't buy them....
I read many topics on transport, I think I'll go with Toslink as jitter on optical links are the easiest to get rid of.
The topology should then be:
In->Receiver->oversampling->FIR->DAC->IV->filter->out.
Then it becomes harder!
Let's use a PLL on the receiver, as I don't want it to add it's own jitter: it should then clock data out at the same rate as the data comes in. I fear of clocking it directly with the word clock, but maybe I'm wrong?
Let's clock the Oversampling and the DAC to the word clock.
What is exactly the frequency given by the word clock? Because it's not the word clock that I need now - it's the bit clock, that depends on the resolution and the oversampling (and of course the sample rate).
How to get this bit clock?
Let's start with these questions, when I'll have solved them I'll go to the next ones 😛
Thank you very much,
Nicolas
Ok some news!
I slept a bit, and thought a bit too.
I now know the typology I want to use:
In->Wolfson SPDIF receiver -> buffer - oversampling -> FIR ->Wolfson WM8740 DAC->buffer- filter->out
The SPDIF receiver just locks itself on the incoming signal frequency. It outputs data at a fs*nb of bits rate. I don't care of the recovered frequency output.
We have some jitter now
Feed it to the FIFO buffer. I'll try to use a large one, even if it should not be necessary as the transport and the DAC system are on the same external master clock.
Then we have the problem of oversampling.
I'm wondering: interpolation or no interpolation? Just clock the output of the buffer at OS*nb of bits*signal freq?
Interpolation is done with an ASRC... Most people suggest not to use it. In fact, smoothing the signal will be done by the output filter so... It's probably better not using it. And it keeps design simpler. Any suggestion?
The other question is: how to make this bit clock.
Make a DIY master clock from synchronous dividers from a high frequency XO, that would output synchronously the word clock and this clock?
Use a PLL frequency mutliplier to recover this bit clock from the word clock? This is the only way to use standard word clock - even if some very expensive ones generate these clocks.
But what about the jitter of this PLL frequency multiplier? I'm not very confident about the jitter of a 24(bits)*8 (oversampling)*44.1 (khz) clock recovered from a simple 44.1 kHz clock....
Maybe may I use a switch to switch between this PLL for use with standard word clocks, and a second input for this high frequency clock.
But if I transmit a 192kHZ audio signal, it leads to a 36, 864 Mhz clock - transmitting this clock on a BNC Coax without jitter doesn't seem very secure.
Wich one leads to the smallest jitter? Recovered clock via a frequency mutiplier PLL or transmitting a high frequency clock?
Thank you very much,
Nicolas
I slept a bit, and thought a bit too.
I now know the typology I want to use:
In->Wolfson SPDIF receiver -> buffer - oversampling -> FIR ->Wolfson WM8740 DAC->buffer- filter->out
The SPDIF receiver just locks itself on the incoming signal frequency. It outputs data at a fs*nb of bits rate. I don't care of the recovered frequency output.
We have some jitter now
Feed it to the FIFO buffer. I'll try to use a large one, even if it should not be necessary as the transport and the DAC system are on the same external master clock.
Then we have the problem of oversampling.
I'm wondering: interpolation or no interpolation? Just clock the output of the buffer at OS*nb of bits*signal freq?
Interpolation is done with an ASRC... Most people suggest not to use it. In fact, smoothing the signal will be done by the output filter so... It's probably better not using it. And it keeps design simpler. Any suggestion?
The other question is: how to make this bit clock.
Make a DIY master clock from synchronous dividers from a high frequency XO, that would output synchronously the word clock and this clock?
Use a PLL frequency mutliplier to recover this bit clock from the word clock? This is the only way to use standard word clock - even if some very expensive ones generate these clocks.
But what about the jitter of this PLL frequency multiplier? I'm not very confident about the jitter of a 24(bits)*8 (oversampling)*44.1 (khz) clock recovered from a simple 44.1 kHz clock....
Maybe may I use a switch to switch between this PLL for use with standard word clocks, and a second input for this high frequency clock.
But if I transmit a 192kHZ audio signal, it leads to a 36, 864 Mhz clock - transmitting this clock on a BNC Coax without jitter doesn't seem very secure.
Wich one leads to the smallest jitter? Recovered clock via a frequency mutiplier PLL or transmitting a high frequency clock?
Thank you very much,
Nicolas
- Status
- Not open for further replies.