DC coupling biasing/switching problem -what's the solution?

With this circuit, I need a steady DC voltage out of the second opamp (I'd have preferred 4V, but that said, not too fussed what the DC level is , just so long as it's steady!) But what I'm getting at the moment is the DC level stepping up/down to a different DC level when the 'polarity invert' jfet is switched on/off.

I guess that 3.9V at the +ve input to the first opamp (pin 3 ) is the root of the problem - presumably from the bias current flowing through R1 causing the bias voltage to drop .01V across r1 ....so I really need a way of making that pin 3 a solid 4V DC (the problem here is my main supply rail is not regulated so I can't use a simple potential divider off that to present 4V at the +ve pin 3 of the first opamp)

Top tips gratefully received!.

All voltages are DC levels (the AC signal is not important here)

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2008-01-08 11:51 pm
Sorry, but what is this circuit supposed to do?

Why does it say +4V all over the place? Where's that coming from?

Why is R5 only connected at one end?

Do the opamps have a single or dual rail supply?

Tell us what the circuit is supposed to do. Invert the polarity of an AC signal when you power the jfet? (I got that from the text, not the circuit). It won't do that. As it stands it's just mad. Not in a good way. And it doesn't fit on the screen.

The 4V is a virtual earth (sourced from a low impedance regulated source - I left that bit out to save on clutter)

The circuit inverts the AC signal (this bit does in fact work - & not sim'ed, but real on breadboard). it's the equivalent of this...


R5 is connected both ends (the dot may be missing at the left hand side, but it connects - in eagle it's definitely connected without the dot)

It's single supply.

The circuit fits my screen!

The cicuit ain't that mad (cos it works:) ), I've just got a bit of DC level stepping going on when the jfet switches in/out.
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But my overall circuit's reference voltage is 4V (ie the '4V' at the bottom of the schematic), albeit the voltage drop across the resistor R1 makes this 3.9V at pin 3.

So the hub of my line of questioning is - how do you design a setup like this to guarantee a required reference voltage at the +ve non inverting pin (because obviously it's this DC bias level that will appear on the opamp output pin).

I'm figuring the traditional way is a potential divider from the rail to ground & then feed the potential divider 'junction' into the non inverting pin. That way the divider could be constructed to ensure 4V is present (vs the 3.9V there is at present). This would then put 4V on the output, ensuring that when the fet switches, there's no variation in DC.

But like I say, my supply line isn't regulated....therefore as the rail wavers slightly so will that DC bias & the potential divider junction.

hey ho, looks like a rejig involving a regulator at the front end of that first opamp! (btw: I don't want to use a cap to separate AC & DC, as I'm experimenting/learning wrt DC coupling of amps)
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As you are using JFET input opamps you should be getting very little offset from input currents. You are using TL074 as the circuit says? There could be up to 10mV input offset simply from JFET mismatch, and this is being amplified by the gain of 10 in the first opamp - this is where your 100mV offset comes from. You could use TL071, which has an offset adjust. Or inject an adjustment bias yourself from a resistor attached to a potential divider. The offset may change slightly with temperature.

You are learning why people don't use DC coupling except when unavoidable!
There could be up to 10mV input offset simply from JFET mismatch, and this is being amplified by the gain of 10 in the first opamp - this is where your 100mV offset comes from.

but the input pin (pin 3) already has 3.9V on it - so I don't think the 100mV offset is coming from the gain? (I'd thought one of the rules of opamps is that whatever you DC bias the +ve pin at, will be replicated at the opamp output - & that's what is happening ...ie 3.9V is appearing at the opamps input pin (pin 3), so that's what's being presented on the output pin - it was worse with a higher value R1 - ie something like 3.6V at the input/ouput of the first opamp)

So the nub of this, is how to get 4V on the input pin 3 when my reference voltage is just 4V!
The output of an op-amp is equal to the input reference, plus gain times (input signal plus input offset). If you are really dropping 0.1V across the 4.7K bias resistor then you are not using a healthy TL074. Such a drop would be high even for a bipolar opamp. I assume you measured this with a DVM - an old-fashioned analogue meter would load the circuit and give a false reading.

Things to check: is the 4.7K really that, or much higher?
Is it really a genuine TL074 (i.e. a JFET input opamp), or something else (perhaps a fake?). There are counterfeit opamps around. JFET inputs are fairly robust, but could it have been damaged by static electricity when you built the circuit?

Choosing equal input resistances is useful for bipolar input amps, but not necessary for FET inputs as the bias current is so small.
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I have heard of people remarking 741 opamps as the latest fancy opamp with the same pinout, and they might not even have been very good 741s! TL074 is not particularly fashionable so less likely to be counterfeit, but the modern chip foundries making these generic devices are not always as careful as the original manufacturers. Even official distributors can sometimes get conned by dodgy businessmen from some of the farther corners of the world.

You seem to have 20uA of input current. This would be way out of spec even for a 741, so it could be a bad batch of something (possibly even TL074).