@dWhitney Did you use exactly the type for logic parts? It must be HCT type. If is something different (like AHCT or ACT or HC or LS) it will not work 😢
I highly recommend for using CPLD converter here. You can do it easily: https://electrodac.blogspot.com/p/i2s-to-tda1541a-converter-tutorial.html
That way you bypass all the logic (you can cut out the logic ICs (with pliers, pin after pin) and glue the CPLD converter on top of that and use a few wires to connect it. It will 100% work bit-perfect 😉
I highly recommend for using CPLD converter here. You can do it easily: https://electrodac.blogspot.com/p/i2s-to-tda1541a-converter-tutorial.html
That way you bypass all the logic (you can cut out the logic ICs (with pliers, pin after pin) and glue the CPLD converter on top of that and use a few wires to connect it. It will 100% work bit-perfect 😉
Miro, is it simple to remove the stop clock option for the TDA1541A in silmutaneous mode, VHL code, please ? Or does it need a complete rewriting?
@diyiggy Do you need only a few additional BCK cycles? If so, you can add the cycles here:
https://github.com/c2titan/I2S-simultaneous-TDA1541A/blob/main/MT02_TDA1541A_I2S_test.vhd
Line 152: if (cntOB >= 2) AND (cntOB < 18) AND (inLRCK = '1') then
if you change 18 to 20, you will get +2 BCK ... I am not sure what happens if you change it to 34, but you can try 😀
https://github.com/c2titan/I2S-simultaneous-TDA1541A/blob/main/MT02_TDA1541A_I2S_test.vhd
Line 152: if (cntOB >= 2) AND (cntOB < 18) AND (inLRCK = '1') then
if you change 18 to 20, you will get +2 BCK ... I am not sure what happens if you change it to 34, but you can try 😀
CPLD heals the logic pain 😉 I just regretted not using it from the beginning for complicated logic projects.
If I had known it was like that, we would never have returned Trieste to Italy 🤣 🤣 .
Let's try it, but before that, pull out the HV from under R12 and connect it immediately to R1.
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Thanks miro, unluckilly I have no scope to check that and am not confortable to model from hard to VHL it after !
It is to try to implement it in order to try Thorsten Loesch reclocking after. A guy here Raptorligthning did it in the TDA1541A big thread (if I remember we talked about that here already), but the FGPA is the other brand we talked and 2.5 x 2.5 mm square size... Hence your bigger size FGPA is only what I can solder with flux but not littlier (I checked there is no through hole FGPA anymore, ahahah).
so if you say it stops the stops clock, I believe you ! 😀
I thought I would share an interesting article on capacitors that I came across: https://keith-snook.info/capacitor-soakage.html.
ok, let's go!
so, this is untested, for those who want to try... welcome !
It will last very very long before i try this...
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@dWhitney, I have an identical experience with the logic on the TDA1541A. I think one of the problems is the xor IC2B, because it adds 1 clock before DATA, followed by 16bit DATA, a total of 17 bits. That one clock in front of DATA always has a high level. It works well with CPLD.
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This Violet one burst is LE. But this LE is instructing DAC to convert datas alrady stored in register (by the BCK). So this LE is for the data prior to LE event, does not visibile on the picture...
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The datas and BCK visibile on the picture are for next LE event, that coming in time, and that LE is not visibile on the picture...
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And take a look at the LE for TDAs in Time Simoultaneous mode
They are different from AD/PCM dacs one is with fallen edge and other is from rising edge of LE
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Also for TDAs in TS mode, MSB has to be inverted form Value in I2S. Check MSBs for L and R channel too vs MSBs in I2S bus...
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Please post picture with 2 LE events. This will be for one Sample rate period...
And for two picturs maginfied around tese LE
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BUT from the last picture LE go to sample happening before one data bit stored?
For one channel.
.TS mode has 2 separate channel datas - incloude booh in the picture?
And for two picturs maginfied around tese LE
.
BUT from the last picture LE go to sample happening before one data bit stored?
For one channel.
.TS mode has 2 separate channel datas - incloude booh in the picture?
I think I found a solution, the data channel was shifted too far to the right by one clock. Now the signal is not perfect, but it works much better and there is no DC-offset at the output. Maybe it would be better with faster shift registers.
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Hi,
possibly make a non stop option in order to use reclocking ater it near the TDA1541A (T Loesch inputs on the TDA1541A long thread) ?
possibly make a non stop option in order to use reclocking ater it near the TDA1541A (T Loesch inputs on the TDA1541A long thread) ?
