DAC AD1862: Almost THT, I2S input, NOS, R-2R

This is a DAC I build with a friend, Alex Weizman (famous ebay JFETS seller), PCB designed by Alex. You can see, 3 floors of AD1862 on each channel.
I/V based on Borbely hybrid (6N1P input differential), all regulators on board. The HV regulators (24V 🙂) are Borbely discrete and the low voltage regulators are opamp based (also a Borbely style but standard). Noisefloor about 3uV from 1hz to 20khz, not weighted.
Linearity about half a db up to 18bits, about 1db at 19bits. More or less accurate up to -114db.
When I have time I will send some measurements. The DAC sounds really good. I must say, the PCM63 is more linear (in linearity test) even without trimmer calibration (as implemented in Parasound DAC). To handle offset we add servo for I/V.
 

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Although one can see in the picture QA401 is hiding but the above tests with COSMOS. Noise is measured by first amplifies noise by Brookdeal 431 LNA then divided by its 60db gain. That is to be sure on measurement. Both the COSMOS and QA401 show more or less the same noise number.
 
@gaycoh You will need to shorten the sample size (word length) and make it simultaneous in the converter (so the CLK is reclocked and clock the signal into both DACs simultanly), (standard stereo I2S word length is 2x32bit).

example:
BCK frequency from standard stereo I2S: 48kHz * 2*32bit = 3.072MHz
if this BCK is not reclocked and is used directly for the x16 overclocked AD1862: 3.072MHz * 16 = 49.152MHz --- way over limit (limit for the AD1862 is 17MHz)
converter (CPLD or FPGA based) can store and prepare DATA and create reclocked CLK for DAC, then it does look like this: 48kHz * 20bit * 16xFS = 15.36MHz for each DAC (both DACs are clocked and latched together)
... it is all only about understanding how the frequency is changed and the frequency limits 😉

PCM63 has higher quaranted frequency (25MHz is guaranteed) and higher frequency can also work (but some bits may be missing or skipped) - I do not recommend doing this large oversampling without checking how many MHz the converter has
Somehow I did not understood, you actually answered fully my original question. Thank you!
I wonder if at the times of AD1862 there was a digital filter that support X16 with 20 bits word length.
 
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@merlin el mago If you want DIY it: #2909 ... or you can buy something ready made from aliexpress 🤣
Sorry for replying late:
there are much better wat to have I2S (or any other) format selector,
many digital IC has one input pin called ENABLE (EN) could be positive or negative does not matter.
with that pin Ypu can switch on-off the compleat line.
And
If You are using digital isolator ICs, they almost all has EN option.
so in the same time You can achieve digital isolation + selector option.
And it is less complicated, but maybe slight more expensive?
Best way is to use single IC isolators, but it could be isolators with 4x inside.
For every I2S input one 4x isolator is enough.
optionally it could be done re-cklock of output I2S bus,
with 3x double flip-flop and have negative data for balanced operation...
.
I am doing that way for years and working very good and stabile.
 
If you have I2SOVERUSB you can prepare files by Matlab, you can use REW generator, you can upsample by midi on Mac or mix on Windows
Of course, most of us who built on AD1862 are working NOS and no music exists on 768K (maybe even not 384K). Classical benefits of upsampling is clear from technical point of view, but not necessarily that inherent THD are not worse in higher sample rates.
 
I have the DDDAC (8xPCM1794 NOS) for many years, with a WaveIO USB card. I noticed differences in the sound when I do the upsampling in the player (I use Album Player and others), but nothing major. I practice 2x upsampling to move the noise to high frequencies where it is met by 1:1 line transformers which mostly eliminates it. 384kHz sampling rate is practical limit for DDDAC.