Current feedback headphone amp

anli said:
Try to move T12/T11 collectors to T13/T14 emiters respectively. Such way you will reduce AC part of Vce for T11/T12. Some resistors values rearrangement is needed, of course. The same idea may (must?) be applied to (pre)output stages.
Yes, but I don't have much voltage and also _how_ much will I reduce?

In order to get good performance the R10 and R11 must be kept as low as possible, preferable zero ohms!
 
peranders said:

Yes, but I don't have much voltage and also _how_ much will I reduce?

In order to get good performance the R10 and R11 must be kept as low as possible, preferable zero ohms!

AC part of T12/T11 Vce will be virtually null. I don't see any reason to make R6/R7 (R10/R11) as low as possible. There isn't one :)

Such way amp's Rin will be much linear (try with non zero Rout signal source) and input (preoutput) stage will have less THD.
 
Try with, say, 30K output resistance signal source - as for input linearity and THD. And measure input buffer power dissipation deviation in both case - as for input buffer thermal distortions.

P.S. Of course, I don't insist on anything. No more rather "I would modified this topology this way".
 
peranders said:
I have done some more simulations and they don't show anything which can confirm what you are saying. Remember also that I have extra stiff current sources as emitter loads.

Probably at this concrete case (with rather small Vce AC part for input transistors) suggested way hasn't such advantages as at cases with high AC input voltage. In my amplifier (follower) under designing (at PCB making stage now) such collector connection has evident advantages in sim:

http://gaydenko.com/um/schematics17.png

I'm sure you will extract the same topology from details :)
 
I have taken a peek at your homepage and I see that you succeed to get much more dynamic range in your FFT plots. How do you do it? Your settings?

I see also that you have many different variations of your NFB design and I see also a couple of pictures. I'll gather that your idea is somewhat tested in real life?

Your 50 nH inductor, this is for simulation I suppose? But does this equavalent circuit look like this? Hardly purely resistive at high frequencies?

Noticed one other thing: Your softstart has 100 ohms in series with 0.47 uF. Make sure this resistor can handle transients from the mains. I use 470 ohms/ 0.6 W metal film. This resistors lasted 10 years before it was worn out. Now I have four 120 ohms in series.
 
Hi both Per-Anders and Anli,

you both have spectacular complex designs which looks interesting at least for the eyes of an engineer! :)


Anli,

I wonder a bit about your schematics you attached, what is the purpose with cascoding Q3 and Q5, I dont see any of the classical advanatges with cascoding here like Miller cap isolation, power dividing, voltage limits of one device etc.?


Cheers Michael
 
peranders said:
I have taken a peek at your homepage and I see that you succeed to get much more dynamic range in your FFT plots. How do you do it? Your settings?

I see also that you have many different variations of your NFB design and I see also a couple of pictures. I'll gather that your idea is somewhat tested in real life?

Your 50 nH inductor, this is for simulation I suppose? But does this equavalent circuit look like this? Hardly purely resistive at high frequencies?

Noticed one other thing: Your softstart has 100 ohms in series with 0.47 uF. Make sure this resistor can handle transients from the mains. I use 470 ohms/ 0.6 W metal film. This resistors lasted 10 years before it was worn out. Now I have four 120 ohms in series.
1. I use LTspice for sim. Just turn of all compression options and use 65536 samples, Blackman window.

2. This is balanced amp. Preamp (without NFB, with own PS) is made. Follower PS with it's softstart is made. There isn't uploaded overall final PS softstart schematics, but timer block is here: http://gaydenko.com/um/ps/softStart-03.png (do not confuse PS softstart and follower softstart/PS-voltage-inspector)
As I have said, follower is under making PCB stage. Final bridge half is here (some values are slightly changed): http://gaydenko.com/um/pcb/schematics.png

3. Inductor is (well, will be) real 20-30 turns around gate resistor.

4. All these is OT, I think :)
 
Ultima Thule said:

...
Anli,

I wonder a bit about your schematics you attached, what is the purpose with cascoding Q3 and Q5, I dont see any of the classical advanatges with cascoding here like Miller cap isolation, power dividing, voltage limits of one device etc.?


Cheers Michael

The aim is very simple: eliminate dissipated power deviation for Q5:

- Q3 makes Vce(Q5) const
- Q7 makes Ic(Q5) const.

It is important to eliminate thermal (memory) distortions: Q5 base-emiter is outside NFB loop. As a side effect, such linearization of Q3 mode reduces THD about 20db :)
 
Ahh, yes of course, now when you remind me of that I see your schematics in an other light!

Actually I see other transistors too coupled in such way that the thermal distortion will be minimized, it seem to be a red line in your design.

Tell me, isn't the gains with optimising the thermal distortion mostly found in a very low frequency area, say up to couple of hundred Hz or so?

BTW, interesting that you use IRFP140N/9140N in the output stage, I actually googled around on IR's webbpage looking for FET's around 50-200 volts last week and found especially these FET's mentioned looking interesting at least on the datasheet, I guess you have som practical experiences with these, what is your thoughts about them?

Sorry if I'm going off-topic, PA?

Cheers Michael :)
 
Ultima Thule said:
Ahh, yes of course, now when you remind me of that I see your schematics in an other light!

Actually I see other transistors too coupled in such way that the thermal distortion will be minimized, it seem to be a red line in your design.

Tell me, isn't the gains with optimising the thermal distortion mostly found in a very low frequency area, say up to couple of hundred Hz or so?

BTW, interesting that you use IRFP140N/9140N in the output stage, I actually googled around on IR's webbpage looking for FET's around 50-200 volts last week and found especially these FET's mentioned looking interesting at least on the datasheet, I guess you have som practical experiences with these, what is your thoughts about them?

Sorry if I'm going off-topic, PA?

Cheers Michael :)

It's my first attempt of DSM-ing (Do Something Myself, (c) anli :) ) after long long years without any soldering.

As for fighting against thermal distortions (they are indeed up to couple of hundred Hz) - there is interesting site ( http://peufeu.free.fr/audio/memory/ ) and interesting (in Russian) article which inspired me to this "thermal war".

As for IRFP140N/9140N - it isn't more rather some pragmatic reasons: cost, availability, SOA. So, sorry, nothing experience.

Indeed, I think we are inside d-e-e-e-e-p off topic. After finishing the amp I'll prepare English page about the amp and will notify the forum. Probably, it is better to switch to private mailing now :)