Yes, but I don't have much voltage and also _how_ much will I reduce?anli said:Try to move T12/T11 collectors to T13/T14 emiters respectively. Such way you will reduce AC part of Vce for T11/T12. Some resistors values rearrangement is needed, of course. The same idea may (must?) be applied to (pre)output stages.
Yes, but I don't have much voltage and also _how_ much will I reduce?
In order to get good performance the R10 and R11 must be kept as low as possible, preferable zero ohms!
For page 1 - R10, R11 probably? OK, they are inside FB loop. R6/R7 are beyond one.peranders said:R6, R7 is a part of the input buffer. Only R11, R12 is involved in the current feedback circuit.
peranders said:I have done some more simulations and they don't show anything which can confirm what you are saying. Remember also that I have extra stiff current sources as emitter loads.
1. I use LTspice for sim. Just turn of all compression options and use 65536 samples, Blackman window.peranders said:I have taken a peek at your homepage and I see that you succeed to get much more dynamic range in your FFT plots. How do you do it? Your settings?
I see also that you have many different variations of your NFB design and I see also a couple of pictures. I'll gather that your idea is somewhat tested in real life?
Your 50 nH inductor, this is for simulation I suppose? But does this equavalent circuit look like this? Hardly purely resistive at high frequencies?
Noticed one other thing: Your softstart has 100 ohms in series with 0.47 uF. Make sure this resistor can handle transients from the mains. I use 470 ohms/ 0.6 W metal film. This resistors lasted 10 years before it was worn out. Now I have four 120 ohms in series.
Ultima Thule said:
I wonder a bit about your schematics you attached, what is the purpose with cascoding Q3 and Q5, I dont see any of the classical advanatges with cascoding here like Miller cap isolation, power dividing, voltage limits of one device etc.?
Ultima Thule said:Ahh, yes of course, now when you remind me of that I see your schematics in an other light!
Actually I see other transistors too coupled in such way that the thermal distortion will be minimized, it seem to be a red line in your design.
Tell me, isn't the gains with optimising the thermal distortion mostly found in a very low frequency area, say up to couple of hundred Hz or so?
BTW, interesting that you use IRFP140N/9140N in the output stage, I actually googled around on IR's webbpage looking for FET's around 50-200 volts last week and found especially these FET's mentioned looking interesting at least on the datasheet, I guess you have som practical experiences with these, what is your thoughts about them?
Sorry if I'm going off-topic, PA?