Can I have some comments on this design?

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Hi there,

I'm about to get the ferric chloride out and make a few boards up, and before I do I'd appreciate any comments on the design and layout atached. in return they are placed in the public domain, for what they're worth ;)

It's intended for 100W into 8R. The DC rails will be +/-50V

I think the design is fairly conservative - it's based on a dev board I made with the ability to try out a lot of different ideas; my conclusion was to keep it simple. It fits on a standard 100x160 eurocard and the only external components are the output power transistors (possibly some ballast resistors for them) and OP transistor d-caps (these will be wired- point-to-piont with their own ground).

I want to use low voltage-high performance transistors in some places, and I'd be really interested in any comments about start-up / fault etc conditions that might over-volt them. I'd like any suggestions for more suitable transistors for the LTP too...

Also If I've done anything silly ;)

Cheers,
 

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Hi Carlos,

The three transistors on each side of the LTP are after a mic amp I did with multiple supermatched pairs on the front end; depending on testing I may only fit one or two of them. It almost seems like something for nothing in terms of noise though.

I have built a fairly rough prototype of it (with PNP transistors in Q15/17...) and it works; step response and FFT looks good, but once I get the PCBs done I'll take it into work where I have an AP and let you know.
 
Hi,
The reason for multiple transistors in the LTP is noise reduction.

Noise in this type of design is pretty much dominated by the input transistors; specifically by their base spreading resistance. Fitting three in parallel reduces this resistance by 2/3, and so noise should be reduced by 1/sqrt(3). Doesn't quite work that well in practice, but the reduction in noise is useful, given the cost.

The other places where there are two transistors in parallel are option fits - I was not sure whether I would want a TO92 or TO126 package in these positions so I've dual-pitched them to give me some options on transistor choice when I'm testing.

Cheers,
 
Atomicplayboy,
the input stage is to my liking, but I´m not a fan of paralleled devices. Noise is just one of about 113 conflicting factors. JFETs have the right properties for this job, offering a much wider dynamic range (partially due to lower noise). In my view, a higher LTP current and a base resistor for Q9, Q15, Q17 would be beneficial. The value of C16 is excessive. I would also reduce the gain by a resistor across the output and refer the cascode voltage source to the emitters. Are R36 and C26 necessary?
 
They are for cascode, right?

Tom

You are right and it is obvious that you are very expertised; but to understand also the other non expertised people, please let me to add a little explanation, as well to place some questions.
Cascoding is used for the exchange of the impedance and bandwidth between the input and output of a circuit. A such stage, consisted from a common-emitter stage followed from a common-base stage. Because the common-emitters are PNP type (the bunch of transistors consisting the LTP) and their collector must be connected to the emitter of common-bases (Q15-Q17) it is obvious that they must be PNP also. Thus, the high impedance is shifted to the inputs of the LTP and the gain is shifted to the common-base stage. The main problem which resolved, is the effective Miller capacitance of the common-emitter stage which limits the bandwidth. Cascoding eliminates this.
I don't know if the purpose of cascoding in this circuit it is the above. From my experiments, i have found another one thing: The positive rail supply ripple, is eliminated completelly by the CCS consisted from Q16-Q19. I don't know why the Q18; Cascoding again? please explain me. Instead, in the collectors of current mirror it exists the negative rail supply ripple which is transfered directly to the base of Q21. Of course, after the effective collector of the bunch of transistors consisting the VAS, the ripple is eliminated. Q24 thru Q25 seems like another one constant current source with local feedback on Q25 thru R27. Unusuall scheme.
My question is this: Can Q15-Q17 offer a help for the negative supply rail ripple rejection?
I ask your forgiveness for any mistake in my explanation. My knoweledge is restricted in general electronics; please correct my mistakes and give me a little explanation for the "why?"

Regs
Fotios
 
Hi,
Thanks for all the comments - sorry if this reply is a bit disjointed!
I've also updated the schems/board (atached)...

Pingrs, you're dead right about the pads - I've now made all pads except the TO92's larger, and I've reduced the drill size on the TO92's. I've also put extra copper around the TO126 pads as they'll have to support a heatsink - the board now looks much more robust to me. What do you use for single-sided pads by the way?

Lumba Ogir, I also wondered about increasing tail current on the front end (since I've got more area of silicon thanks to the paralleled PNPs) to get the same current density - I think this is something I'll have to experiment with (would your thinking be to run at 3x the current ?). I don't want to dismiss the idea of using JFETs here, but I think that will have to wait for the next version of this board (If you can point me in the direction of some part numbers I'll have a look though).

I found a mistake in the front end too, I started with single PNP transistors and 100R degeneration, and didn't increase the degeneration resistors when changing to a sziklai. R16 and R17 should be 270R, which brings gm back down to a sensible level.

Base resistors for Q15, Q17 - I didn't include these thinking that by joining the bases directly together the noise generated by the LED bias source gets delivered more equally onto both arms of the LTP; can you elaborate on what putting resistors here would achieve?

Resistor in the base of Q9 - there will be a small noise penalty from this. Is your thinking to match the AC impedances into the bases, or for protection? I've added provision for this anyway now since I can always link it out.

R36 is a wire link - I try not to use them but the LTP structure is difficult to exit from on the board. C26 is intended to make sure that both arms of the LTP see the same capacitance (C26 is to match C20). I'm not sure if I'll fit it or not, but I like the symmetry of it :)

C16 - Agreed - what was I thinking :) 100p sounds better.

Fotios, my main reason for adding the cascode was to reduce the Vce of the transistors in the LTP, hopefully to allow the use of better devices rather that the fairly crappy high voltage type currently shown on the schem. I don't think the cascode gives much improvement if any to the linearity of the input stage in isolation since the voltage swing at the collectors on the LTP is quite small, though it can't do any harm to have it.

I do think it's possible to reduce negative ripple using the cascode by connecting the dominant-pole compensation cap above it (from Doug Self's book - forgot about that trick); I've provisioned for this now, though I'm a bit wary about making the compensation connection go all over the place to get there.

Anyway thanks again, any further thoughts much appreciated!

Cheers,
 

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Fotios, my main reason for adding the cascode was to reduce the Vce of the transistors in the LTP, hopefully to allow the use of better devices rather that the fairly crappy high voltage type currently shown on the schem. I don't think the cascode gives much improvement if any to the linearity of the input stage in isolation since the voltage swing at the collectors on the LTP is quite small, though it can't do any harm to have it.

I do think it's possible to reduce negative ripple using the cascode by connecting the dominant-pole compensation cap above it (from Doug Self's book - forgot about that trick); I've provisioned for this now, though I'm a bit wary about making the compensation connection go all over the place to get there.

Tom, from that i know, for reducing the Vce usually it is used the cascade topology, which is most simple from cascode. For better devices for the input stage, take a look e.g. in Toshibas 2SA970-2SC2240. I have tried these in an amplifier with +/-70V supply rails, and i have not, no one problem after 1 year of operation. Also, these transistors does not have the need of a high tail current like MPSAxx. From my experiments (i use almost the same input topology in my amplifiers like you) i have ascertained that a tail current above 3,5mA it is useless for the 2SA970 (PNP). Instead, when i used MPSA56 or 2N5401 there was the need of a tail current of 6mA at least. You can find Toshibas 2SA-2SC very easy in enough on-line stores in Europe. I bought those before 1,5 year from RS Components offered in small antistatic bags of 5 pieces and the transistors was ORIGINAL Toshiba "made in Japan".
I know that current mirrors used mainly to balance the collector currents of LTP to eliminate the DC offset in output and sincerelly, i had not idea that the trick of connecting the Cdom above cascodes is reffered on D.Self book. I have this old book from 1998, but i have not study it in detail never. I spend my life on the workbench with experiments (what a stupid thing!) to find things that are ready offered in my dusty books.

Regs
Fotios
 
I've got an output stage question...

I'm using a CFP output stage with 2SD669 as a driver and a parallel pair of 2SA1295's on the top half, and their compliments on the bottom.

I wonder if there's a way to calculate the optimum value for the resistor I've made up from R50, R51, R52 (I came to this value experimentally). I know that lower is better because it improves the switchoff speed of the output transistors, until loading on the previous stage gets too high and this distortion dominates. I'd like to be able to calculate the best value rather than do it empirically.

Cheers,
 
Hi Fotios,

I actually have some 2SA970's I picked up to experiment with - they are really good parts and I might well switch to them on this design. I'm a big fan of Japanese transistors :) It kind of anoys me that most small-signal amplifier datasheets don't come with the noise-figure plot showing the optimal operating current / source impedance; it seems like something that everyone using the part would want to know.

The trick with connecting the compensation cap via a cascode transistor I think was 'invented' by Mr Self; I've never seen it anywhere else, but when you look at it it does make sense. I just worry that there are other drawbacks to this due to the larger area of the Cdom loop. The other thing he suggested was decoupling the collector of the emitter follower (Q21 in my design) tightly to the Vee rail, that is the collector has an isolated ground trace that hits the d-cap to Vee then goes into the groundplane. I don't think I can do this with the layout as it is but I might look at it in future.

I also like to experiment, but it's interesting to read the opinions of other engineers; even if you dissagree with their approach they can give you good ideas and new things to try. Lol I find it less frustrating that way!

BTW I use www.cricklewoodelectronics.com for hard to source / obsolete transistors in the UK - they have *everything*.

Cheers,
 
Atomicplayboy,
shifting to JFET would probably be the greatest improvement you could make. The need for P-channel type complicates things somewhat. 2SJ103 would be very nice, or 2SJ74.
Base resistors (also for Q18, Q19) are required for stability, which is at least as desirable as low noise (to me).
 
Lumba Ogir,
I've added the resistors as you suggest, though I'm not sure what the instability mechanism you've spotted is - coupling between the sides of the LTP at HF through Ccb of the transistors?

Thanks for the JFET part suggestions; I can get 2SJ103's easily so I'll pick some up to put on the curve tracer and have a look at. I've never had that much luck with JFET input stages in the past - low gm (so not much scope for local NFB), noisy with low input impedances (especially P-type), high parasitic capacitance and lots of variation from one device to the next. I know there are better parts on the market these days though.

What's the bigest selling point of JFETs in an LTP in your opinion?

Cheers,
 
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Lumba Ogir,
I've added the resistors as you suggest, though I'm not sure what the instability mechanism you've spotted is - coupling between the sides of the LTP at HF through Ccb of the transistors?

Thanks for the JFET part suggestions; I can get 2SJ103's easily so I'll pick some up to put on the curve tracer and have a look at. I've never had that much luck with JFET input stages in the past - low gm (so not much scope for local NFB), noisy with low input impedances (especially P-type), high parasitic capacitance and lots of variation from one device to the next. I know there are better parts on the market these days though.

What's the bigest selling point of JFETs in an LTP in your opinion?

Cheers,

Try Jfet/Bjt cfp, works ok. To obtain higher gm with jfets just parralel two or more of them.
 
Atomicplayboy,
the CFP is expressly prone to oscillation and the cascode can exacerbate that. The oscillation occurs at very high frequencies, inducing distortion. Low source impedances can cause instability too.
Being a transconductance amplifier, JFET is to be used for every reason (always cascoded). The 2SJ103 has small capacitances (due to low Gm), while the reverse transfer capacitance of 2SJ74 is disturbingly large. JFETs need to be checked and matched for Idss. The voltage gain is (desirably) low because of low output impedance, set by the input impedance of the cascoding transistor, that mainly provides the gain of the stage.
Some suitable types for voltage amplification:
2SC2911/2SA1209
2SC3600/2SA1406
2SC3601/2SA1407
2SC3423/2SA1360
2SD1609/2SB1109
 
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