BITs and SINAD on ADCs

[SemperFi]

Not necessarily audio related...
Just a general question regarding ADC specs. For example a 16bit ADC should have dynamic range and SINAD of 96dB. Being realistic in practice not all bits are really used, often we lose at least 1bit, so a spec'd 16bit ADC is really 15bits, so we are down to 90dB.
But there are so many ADCs spec'd at a given bit resolution but their SINAD and dynamic range is much lower than 20log(2^bit). In the headers they can state 'true 16bit' but just a few lines down in the text it will say SINAD of 80dB, which is only 14bit.
What's the general expectations we can have regarding spec'd bit resolution and actual resolution?

 

[Markw4]

What's the general expectations we can have regarding spec'd bit resolution and actual resolution?

There is no standard rule that comes to mind. Maybe why data sheets have so much information because of all the ways in which devices can vary. Actually, sometimes the data sheets don't tell the whole story either.

If it matters for a particular application then one might have to do one's own testing to qualify a device and or find out what is needed to design with it.

 

[MarcelvdG]

Not necessarily audio related...
Just a general question regarding ADC specs. For example a 16bit ADC should have dynamic range and SINAD of 96dB.

I already disagree with you here...

An ideal undithered 16 bits ADC converting a full-scale sine wave at a frequency that has no rational relation to the sample rate should theoretically have a SINAD of about 98 dB, 20 dB*log10(2)*n + 10 dB*log10(3/2). The extra term is due to the fact that a sine wave spends more time near its peaks than near zero, so it has more power than uniformly distributed noise with the same peak-to-peak value.

For audio, one would normally want to dither the ADC to make the quantization error sound like noise rather than distortion, and to ensure that details below 1 LSB are not entirely lost. This reduces the SINAD by 10 dB*log10(3) ~= 4.77 dB if it is 2 LSB peak-to-peak triangular probability density function dither, but as triangular dither is hard to make in an analogue way, using Gaussian noise and accepting a noise penalty of about 6 dB may be more practical.

In either case, this SINAD is based only on quantization noise with or without dither. In many practical cases, particularly for oversampling converters with a digital decimation filter, adding a couple of bits to the output to reduce quantization noise is cheap in terms of power and chip area compared to reducing the analogue noise floor. It then makes sense to add a few bits to make quantization noise negligible and let the analogue noise determine the performance.

On top of that there is of course the commercial side. If there is a market for converters with 32 bit output wordlength and 16 bit performance, there will be companies that make them, no matter whether it makes sense technically.

 

[SemperFi]

Thanks for answers. I understand that if an ADC input is divided into 2^X steps, it is not always possible to use all steps, especially the steps at the extremes right at 0 and Vref. But there are so many ADC with dynamic performance that are 2bits below spec, or even more. In cases where ADCs are selected for their actual resolution, it would be better if the datasheet better stated that for example: 14bit resolution ADC using 16bit steps, but I guess I just have to learn better how they work and how they are defined.

 

[Mark Tillotson]

The performance is not necessarily indepedent of frequency, a converter can be true 20 bit at DC, yet a smaller ENOB at frequency. With sigma-delta converters this is likely, and the noise floor is not flat either, being noise-shaped.