Bias current influencing compensation?

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Hi everyone,
I'm newbie in solid state amplifiers design, and I've never mounted one, but I'm simulating a design based on one design I've seen in Bob Cordell's book "Designing Audio Power Amplifiers", but I've found a weird problem in single pole compensation because when I try to raise the bias current passing thru the output devices the phase shift begins to roll to the dangerous zone, this also happens when I lower the testing temperature is this normal?
I've tried to change the values of Rgate resistors, the vbe multiplier topology, and the Zobel network, nothing helps, the only way to solve the phase shift problem is to put the devices in cut off region, but this raises distortion and causes overshooting at high frequencies.
I tried to remove the muting, thermal shutdown and output protection circuits, but the result is the same.
Bob Cordell's formula:
CMiller = gmLTP/(2*pi*fH*Acl) [F]
I've tried this formula, using the recomended 500 kHz, the value I've got is 22 pF, but I've to use 56 pF or more and I don't understand why.
I'm simulating this circuit using TINA from Texas Instruments.

Design attached,
Best regards,
Daniel Almeida
 

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