Hmm.. after pondering I-V conversion, a resistor really does seem to be the ultimate solution, with only one major problem - regular audio DACs can't deal with any voltage on their current outputs, so a resistor I-V (ala SDS labs) introduces non-monotonic distortion in the output. However, I deal with video circuitry quite a lot in my day job, so I thought I'd investigate the potential of using a video DAC for audio purposes... 🙂
The TI THS5671A dac runs 14-bit high-current output at 125MHz. It's also affordable. Now, if we oversample 2x for every bit we drop (dithering as we go...), we retain the full resolution of the original data. Starting from 24-bit data and dropping down to 14 bits means we need to oversample 1024x and dither the 10-bits of truncated data into the 14 bit output... dividing 125MHz by 1024 gives us a starting sample rate of just over 122kHz / 24bit. This can be conveniently acheived using an AD1896, which would simultaneously provide jitter rejection. All that's missing is a CPLD to implement the oversampling and noise-shaped dithering logic (which would take a little work, but not too much).
Another nice thing about the THS5671A: it can be configured to give differential outputs into low impedence loads, which is perfect for direct-coupling to a preamp - without a buffer opamp! All that's needed in-between the DAC and the balanced output is a pair of I-V resistors (4 if you count both sides of one channel), one on either side of a passive L-C filter. As long as the preamp's input is in the kohm range, there shouldn't be any problems! Additionally, due to the extremely high sampling frequency, our analog output filter can be a passive LC type with a corner frequency *way* up where it won't affect the frequency and phase response of the audio range much.
Now, i just have to figure out how i'm going to get all these other projects done so I'll have the time to try this out...
The TI THS5671A dac runs 14-bit high-current output at 125MHz. It's also affordable. Now, if we oversample 2x for every bit we drop (dithering as we go...), we retain the full resolution of the original data. Starting from 24-bit data and dropping down to 14 bits means we need to oversample 1024x and dither the 10-bits of truncated data into the 14 bit output... dividing 125MHz by 1024 gives us a starting sample rate of just over 122kHz / 24bit. This can be conveniently acheived using an AD1896, which would simultaneously provide jitter rejection. All that's missing is a CPLD to implement the oversampling and noise-shaped dithering logic (which would take a little work, but not too much).
Another nice thing about the THS5671A: it can be configured to give differential outputs into low impedence loads, which is perfect for direct-coupling to a preamp - without a buffer opamp! All that's needed in-between the DAC and the balanced output is a pair of I-V resistors (4 if you count both sides of one channel), one on either side of a passive L-C filter. As long as the preamp's input is in the kohm range, there shouldn't be any problems! Additionally, due to the extremely high sampling frequency, our analog output filter can be a passive LC type with a corner frequency *way* up where it won't affect the frequency and phase response of the audio range much.
Now, i just have to figure out how i'm going to get all these other projects done so I'll have the time to try this out...
Oversampled Video DAC
It's late, but I think your math is off. You get 1/2 bit per 2X oversampling. I think once you delve into this, you will find it is not that simple, and that CPLD will end up as a minimum, an FPGA, and when you start processing 24 bits at 100MHz, suddenly, it is not so much fun. I would love to hear your thoughts as you progress. I have looked into this before.
You still have issues of jitter. You need to generate that high frequency clock with something. Possibly a custom crystal could be a solution. If you do a PLL, then you will have jitter issues (short and long term).
It's late, but I think your math is off. You get 1/2 bit per 2X oversampling. I think once you delve into this, you will find it is not that simple, and that CPLD will end up as a minimum, an FPGA, and when you start processing 24 bits at 100MHz, suddenly, it is not so much fun. I would love to hear your thoughts as you progress. I have looked into this before.
You still have issues of jitter. You need to generate that high frequency clock with something. Possibly a custom crystal could be a solution. If you do a PLL, then you will have jitter issues (short and long term).
um, i'm pretty sure it's 1 bit per 2x oversampling.. for instance, if we have a single 11-bit sample, we have:
2^11 = 2048 possible values
by oversampling 2x, and rounding down by one LSB, we get two 10-bit samples:
2 x (2^10) = 2^11 = 2048 possible values can be represented.
Unless there's some esoteric bit of logic I'm missing, it seems relatively straightforward to me. Not that keeping all the information really matters anyway if one employs sigma-delta techniques. Sigma-delta tricks might also help do away with some of the jitter issues. Of course you're right that it will take a rather large FPGA/CPLD (same thing in my books) to do the math, and running these things at 100MHz isn't trivial.
I think what attracts me the most to this concept is the possibility of driving line-level outputs directly from the DAC! A low-impedance passive reconstruction filter with no active stage at all is very appealing to me. Imagine, a direct-drive DAC with an output impedance of 37.5ohms or so... you could drive a pair of headphones straight from the DAC!
Unfortunately, I rather doubt I'll get to build this thing, at least in the foreseeable future...
2^11 = 2048 possible values
by oversampling 2x, and rounding down by one LSB, we get two 10-bit samples:
2 x (2^10) = 2^11 = 2048 possible values can be represented.
Unless there's some esoteric bit of logic I'm missing, it seems relatively straightforward to me. Not that keeping all the information really matters anyway if one employs sigma-delta techniques. Sigma-delta tricks might also help do away with some of the jitter issues. Of course you're right that it will take a rather large FPGA/CPLD (same thing in my books) to do the math, and running these things at 100MHz isn't trivial.
I think what attracts me the most to this concept is the possibility of driving line-level outputs directly from the DAC! A low-impedance passive reconstruction filter with no active stage at all is very appealing to me. Imagine, a direct-drive DAC with an output impedance of 37.5ohms or so... you could drive a pair of headphones straight from the DAC!
Unfortunately, I rather doubt I'll get to build this thing, at least in the foreseeable future...
Multiply or divide?
I have one suggestion and one possible design idea for you:
1. Instead of starting at 125MHz and dividing, why don't you start at the sampling rate you need and multiply up to a region of interest?
2. Another way to go would be to use a PC as the DAC. As I recall, the PCI interface can handle up to 64 bits at 33MHz (or in that region). Thus, you can set up a stream 64 bits wide and build 64 summing current sources (same current or not). I believe some manufacturers are looking at something along those lines.
Another alternative is to take an SACD bitstream and multiplex it say 8 ways ... Burr Brown had a PCM1704K (*4 per channel) which did the same thing.
Petter
I have one suggestion and one possible design idea for you:
1. Instead of starting at 125MHz and dividing, why don't you start at the sampling rate you need and multiply up to a region of interest?
2. Another way to go would be to use a PC as the DAC. As I recall, the PCI interface can handle up to 64 bits at 33MHz (or in that region). Thus, you can set up a stream 64 bits wide and build 64 summing current sources (same current or not). I believe some manufacturers are looking at something along those lines.
Another alternative is to take an SACD bitstream and multiplex it say 8 ways ... Burr Brown had a PCM1704K (*4 per channel) which did the same thing.
Petter
How much to oversample per bit gained
Went over the math, nope, you definately need to oversample 4 times to get an extra bit. The math is much more complex than just looking at data and samples. You need to look at how the noise spectra is spread over the sampling bandwidth.
Went over the math, nope, you definately need to oversample 4 times to get an extra bit. The math is much more complex than just looking at data and samples. You need to look at how the noise spectra is spread over the sampling bandwidth.
Petter:
re: #1. - well, i guess that's the other way of doing it. I just wanted to see what the maximum starting sample rate capability might be. 122kHz max xample rate is certainly enough to accomodate 96kHz data...
alvaius:
The calculations in my previous post were for un-dithered data only, so noise spectra do not even play a part. We can represent the same set of values by dropping one LSB per 2x oversampling. By employing dither, we should actually be able to lose MORE than 1 bit per 2x oversampling. Once you introduce dither (and human hearing threshold curves), then yes the math gets a lot more complex, and you will need to employ noise shaping to keep the dither noise out of the bandwidth of interest. This is how sigma-delta and bitstream DACs can get away with using very few bits for actual output with a mere 128x or so oversampling.
re: #1. - well, i guess that's the other way of doing it. I just wanted to see what the maximum starting sample rate capability might be. 122kHz max xample rate is certainly enough to accomodate 96kHz data...
alvaius:
The calculations in my previous post were for un-dithered data only, so noise spectra do not even play a part. We can represent the same set of values by dropping one LSB per 2x oversampling. By employing dither, we should actually be able to lose MORE than 1 bit per 2x oversampling. Once you introduce dither (and human hearing threshold curves), then yes the math gets a lot more complex, and you will need to employ noise shaping to keep the dither noise out of the bandwidth of interest. This is how sigma-delta and bitstream DACs can get away with using very few bits for actual output with a mere 128x or so oversampling.
Oversampling
Please check your math again. I am also talking undithered. You need 4x for 1 bit improvement. This would represent a flat spreading of the noise spectra. Sigma-delta shapes the noise and puts it into higher frequencies that is subsequently filtered out.
Please check your math again. I am also talking undithered. You need 4x for 1 bit improvement. This would represent a flat spreading of the noise spectra. Sigma-delta shapes the noise and puts it into higher frequencies that is subsequently filtered out.
alvaius:
ah, i see what you're referring to... Yes, you are correct, presuming no dither and noise shaping are applied, thereby resulting in a flat quantisation noise spectra.
Naturally, noise shaping would be an essential element of this project... Sorry, i had been disregarding SNR and dynamic range, with the foreknowledge that noise shaping would be applied to move the dither and quantisation noise up out of the audio bandwidth.
ah, i see what you're referring to... Yes, you are correct, presuming no dither and noise shaping are applied, thereby resulting in a flat quantisation noise spectra.
Naturally, noise shaping would be an essential element of this project... Sorry, i had been disregarding SNR and dynamic range, with the foreknowledge that noise shaping would be applied to move the dither and quantisation noise up out of the audio bandwidth.
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