top Project Status (02/14/2021 - 22:57:54)
Project File: LX150.xise Parser Errors: No Errors
Module Name: top Implementation State: Placed and Routed
Target Device: xc6slx150-2csg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
656 Warnings (601 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 4 Failing Constraints
Environment: System Settings
  • Final Timing Score:
86224  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 7,437 184,304 4%  
    Number used as Flip Flops 7,436      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 1      
Number of Slice LUTs 9,792 92,152 10%  
    Number used as logic 8,391 92,152 9%  
        Number using O6 output only 7,422      
        Number using O5 output only 221      
        Number using O5 and O6 748      
        Number used as ROM 0      
    Number used as Memory 1,000 21,680 4%  
        Number used as Dual Port RAM 244      
            Number using O6 output only 8      
            Number using O5 output only 0      
            Number using O5 and O6 236      
        Number used as Single Port RAM 0      
        Number used as Shift Register 756      
            Number using O6 output only 128      
            Number using O5 output only 0      
            Number using O5 and O6 628      
    Number used exclusively as route-thrus 401      
        Number with same-slice register load 182      
        Number with same-slice carry load 219      
        Number with other load 0      
Number of occupied Slices 3,289 23,038 14%  
Number of MUXCYs used 4,948 46,076 10%  
Number of LUT Flip Flop pairs used 10,521      
    Number with an unused Flip Flop 4,075 10,521 38%  
    Number with an unused LUT 729 10,521 6%  
    Number of fully used LUT-FF pairs 5,717 10,521 54%  
    Number of unique control sets 174      
    Number of slice register sites lost
        to control set restrictions
748 184,304 1%  
Number of bonded IOBs 63 338 18%  
Number of RAMB16BWERs 34 268 12%  
Number of RAMB8BWERs 25 536 4%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 2 32 6%  
    Number used as BUFIO2FBs 2      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 8 16 50%  
    Number used as BUFGs 8      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 2 12 16%  
    Number used as DCMs 2      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 586 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 0 586 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 95 180 52%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 6 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 1 1 100%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.66      
 
Performance Summary [-]
Final Timing Score: 86224 (Setup: 69788, Hold: 16436, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 4 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Feb 14 22:01:52 20210600 Warnings (600 new)94 Infos (94 new)
Translation ReportCurrentSun Feb 14 22:02:13 2021021 Warnings (0 new)3 Infos (0 new)
Map ReportCurrentSun Feb 14 22:07:45 2021015 Warnings (0 new)209 Infos (196 new)
Place and Route ReportCurrentSun Feb 14 22:53:30 2021017 Warnings (1 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSun Feb 14 22:54:25 202103 Warnings (0 new)4 Infos (0 new)
Bitgen ReportOut of DateSun Feb 14 03:12:47 2021013 Warnings (13 new)3 Infos (3 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportCurrentSun Feb 14 22:57:54 2021
Physical Synthesis ReportCurrentSun Feb 14 22:07:45 2021
WebTalk Log FileOut of DateSun Feb 14 03:12:49 2021

Date Generated: 02/14/2021 - 22:57:54