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Ian's I2S FIFO Project
This is a wiki to provide an easy to consume index for the Asynchronous I2S FIFO project as designed by diyAudio forum member - iancanada
All intellectual property for the project is Ian's.
The 'basic' form of this project is to provide i2s input (or spdif/AES via interfacing board) into a FIFO buffer to decouple the DAC's local clock from the digital source clock this is then supplied to a board with a high performance clock and re-clocks the i2s output in synch with the high local clock with GHz flip flops. This provides an i2s output with improved jitter performance. Performance of the clock used is critical and clock selection is left to the user.
NB For those new to using i2s, the naming for signals on some boards may be different to what is labelled on the FIFO. The list below shows which signal names are interchangeable:
FSCLK/frame sync clock/LRCK/Left Right Clock/WS/Word Sync
This project consists of a group of boards/projects designed by Ian each able to be used independently or combined to suit user needs/preferences.
Main development thread for all projects captures the discussion throughout the development iterations from the project's inception through various hardware revisions and testing.
Please see FIFO GBIII manual
The current manual shows the signals for J13 on Page 6. The signals for 128*Fs (pin 2) and 512*Fs (pin 3) are related as follows:
// fs128 fs512 fs
// 0 0 256fs
// 1 0 128fs
// 0 1 512fs
// 1 1 1024fs
This is true for all FIFO with v3.80 firmware onwards.
With Si570 the resulting fs is actually double (2*) the above result.
Ian details FIFO firmware revision changes in Post 457. Current GBIII Firmware is V3.80.
Ian posted some measurements comparing FIFO to WM8805.
1. SCK jitter measurements
2. MCLK jitter measurements
3. Measurements of Si570 performance were listed in Post 2259
Ian posted an example of a tested USB source (WaveIO) in Post 1348. He makes some recommendations regarding the configuration of the WaveIO->FIFO depending on different user configurations.
AR2 posted some great photos of his build with FIFO and an ackoDAC in Post 1443. (This is perhaps one of the few FIFOs installed inside an enclosure!)
qusp posted a photo of an initial 'breadboard' of his ackoDAC with FIFO in Post 439. (I think there are more recent photos of qusp's build somewhere, my seaching hasn't found them, yet)
Please see Dual XO Board manual
1. Post 2745 - shows how to convert the dual XO board to run from a lifepo4 battery
Isolator board provides for Si8650 or IL260E to be used for i2s isolation between FIFO buffer and the re-clocking stage. Also provides i2c/generic isolation for DAC control.
The isolator board is in prototype testing stage currently and has no detailed implementation guide, schematics and BoM are provided for reference (links to each revision below). There are alternative i2s and (optional) generic isolator positions as well as alternative LDO positions provided. Feedback on build and SQ impacts of the different isolators are encouraged by those who have built these boards!
Rev 1 isolator board schemtics, BOM etc are here.
Schematics and BOM listed in this post.
Isolator Rev2.5 was the first FIFO isolatore offered pre-assembled. Schematics of the board were posted.
Please see spdif board manual
Details of SPDIF i2s 'backdoor' input modification are detailed in a separate pdf included in the manual zip file linked above. Early details in the development thread are in Post 767.
Documentation from GBIII is available in this document.
FIFO Thread Post 1675 details the Passive Battery Management Board Rev2.0. NB All battery management boards at this time (5/1/2013) have been Rev1.0, Rev2.0 will be provided in a future Group Buy.
Rev2.5 was offered in GBIV, schematic was made available here.
Some DAC chips perform better with higher MCLK speeds than are readily available as crystal oscillators as would be used with the current Single/Dual XO designs. To fill this need iancanada has designed an Si570 board that integrates with his FIFO design to automatically select MCLK frequency and provide re-clocked i2s outputs. This Si570 design will eventual be an optional alternative to the single/dual xo boards with GB offered when necessary quantities are met.
Si570 is a programmable XO/VCXO from Silicon Labs.
Final Si570 user guide for v3.50 which is the first revision of the Si570 board that Ian has offered for GB.
Index of R&D testing and details of the varios prototype Si570 revisions are in the following:
1. Post 913 - ESS 9018 testing with sync mclk from Si570 - post includes selectable sets of frequencies for different DAC types and some discussion on next steps. [more recent details of freq group selection detail in Item 8 of this list]
2. Post 929 - Additional comments & continuation of Post 913.
3. Post 1004 and Post 994 - Image of v2.0 pcb layout and new features in v2 design.
4. Post 1712 details v3 design changes. Highlights include option for inverted mclk per ESS application note recommendation.
5. Post 1530 details the external UART control interface for Si570 frequency selection/notification
6. Post 1606 has some discussion on inverted master clock options.
7. Post 2206 First glance at v3.0 hardware.
8. Post 2222 - details of standalone mode and FIFO mode operation control by the local push button.
9. Post 2240 describes the Si570 configuration for dual mono DAC connections.
10. Power supply options listed in Post 2258 and External regulator options in Post 2259
11. Measurements of Si570 performance were listed in Post 2259
Details of Rev1.5 testing board offer were posted in Post 1626 and all boards are now accounted for by testers.
Schematic for GBIV was posted.
Ian has designed some adapters to suit the Twisted Pear BIII. One adapter provides u.fl pads for the i2s input and the other provides a clock input for using the BIII in either synch or asynch mode.
Manual for these adapters is here.
Clock adapter is described in Post 745.
u.fl adapter is described in Post 743.
Development thread - http://www.diyaudio.com/forums/digit...ver-board.html
The purpose of this board is two fold:
1. NOS operation of R2R DAC's, ie L and R data in the proper format for the separate channel DAC's without resorting to huge amounts of discrete logic, guaranteed datasheet timing requirements and with the Fifo it allows a true DAC master clock operation, less jitter than an S-D transport only much more flexible (i.e. adding a digital anti-sin(x)/(x) filter is just a couple mouse clicks.)
2. Thru the use of computer audio players like Audirvana, Signalyst, Foobar+Sox,XXX High-End, J-river etc one can oversample and create a filter response to one's needs without resorting to "locked in" oversampling of DSP chips and their associated 50+ ps jitter. With the right USB-I2S ahead of the fifo 8x R2R oversampling is entirely open via the PC/Mac/Linux for the first time in history.
Final hardware was presented in the i2s-PCM daughter board thread in Post 461
To allow isolation of the USB ground before the FIFO Ian has provided a prototype 'universal i2s isolator' design in Post #2125
From that post Ian comments that:
For group buy details please see this thread - http://www.diyaudio.com/forums/group...group-buy.html
The details for the most recent group buy are here - http://www.diyaudio.com/forums/group...ml#post3662743
Group buys of boards are organised in batches after reaching minimum qty, please express interest in this thread by adding your name to the most recent list, Ian will provide details when the qty is met then details as per above (which were for GBV) will be posted.
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