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Old 14th December 2011, 07:06 AM   #1
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Default Electronic Parts from utsource

NPN TRANSISTOR 2N3440
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product details:
2N3440 datasheet pdf,2N3440 supplier,2N3440 price,2N3440 picture at UTSOURCE
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2N3440 2N3440
SILICON NPN TRANSISTORSSGS-THOMSON PREFERRED SALESTYPES
NPN TRANSISTOR
DESCRIPTION
The 2N3440, 2N3440 are silicon epitaxial planar NPN transistors in jedec TO-39 metal case designed for use in consumer and industrial line-operated applications.These devices are particularly suited as drivers in high-voltage low current inverters, switching and series regulators.
Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Old 20th December 2011, 04:53 AM   #2
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Post 1s1588 Diode

1s1588 Diode
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1S1585-1S1588
Silicon Epitaxial1 Planar Type
Diode Unit in nun
ULTRA HIGH SPEED SWITCHING APPLICATIONS.
FEATURES:
. Low Forward Voltage : Vf=1.0V (Max.) « Small Total Capacitance : CT=2pF (Max.) . Fast Reverse Recovery Time : Trrs;2ns (Max.)


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Old 20th December 2011, 06:34 AM   #3
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Default bts723gw RON 105mΩ 53mΩ

bts723gw RON 105mΩ 53mΩ
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Smart High-Side Power Switch
Two Channels: 2 x 100mΩ
Status Feedback
Suitable for 42V
Product Summary
Operating Voltage Vbb(on) 7.0 ... 58V
Active channels One two parallel
On-state Resistance RON 105mΩ 53mΩ
Nominal load current IL(NOM) 2.9A 4.2A
Current limitation IL(SCr) 8A 8A
General Description
• N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS 80V technology.
• Providing embedded protective functions
• An array of resistors is integrated in order to reduce the external components
Applications
• ΅C compatible high-side power switch with diagnostic feedback for 12V and 24V and 42V grounded loads
• All types of resistive, inductive and capacitive loads
• Most suitable for inductive loads
• Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
• CMOS compatible input
• Improved electromagnetic compatibility (EMC)
• Fast demagnetization of inductive loads
• Stable behaviour at undervoltage
• Wide operating voltage range
• Logic ground independent from load ground
• Optimized inverscurrent capability
Protection Functions
• Short circuit protection
• Overload protection
• Current limitation
• Thermal shutdown
• Overvoltage protection (including load dump) with external
resistor
• Reverse battery protection with external resistor
• Loss of ground and loss of Vbb protection
• Electrostatic discharge protection (ESD)
Diagnostic Function
• Diagnostic feedback with open drain output and integrated
pull up resistors
• Open load detection in OFF-state
• Feedback of thermal shutdown in ON-state
• Diagnostic feedback of both channels works properly in case of inverse current
Leadframe (Vbb) is connected to pin 1,7,8,14
External RGND optional; a single resistor RGND =150Ω for reverse battery protection up to the max.
operating voltage.
ESD-Zener diode: 6.1 V typ., RST(ON) < 250 Ω,
RST = 850 Ω typ., Rpull up = 12 kΩ typ.
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended
Short Circuit detection
Fault Signal at ST-Pin: VON > 4.0 V typ, no switch off by
the PROFET itself, external switch off recommended!
VZ1 = 6.1 V typ., VZ2 = 63 V typ., RGND = 150 Ω,
RI = 850 Ω typ., RST = 20 kΩ typ., Rpull up = 12 kΩ typ
In case of reverse battery the load current has to be
limited by the load. Temperature protection is not
active
Open-load detection, OUT1 or OUT2
OFF-state diagnostic condition:
Open load, if VOUT > 2.7 V typ. (IN low)
IL(OL) typ. 2μA
An external resitor can be used to increase the open
load detection current
Open load
detection
For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 12) each switch is
protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb disconnection
with energized inductive load all the load current
flows through the GND connection.
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 Mόnchen
© Infineon Technologies AG 2001
All Rights Reserved.
Attention please!
The information herein is given to describe certaincomponents and shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits,
descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body,or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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Old 20th December 2011, 08:33 AM   #4
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Default tle6240gp Short Circuit Protection

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tle6240gp application circuit
tle6240gp application notes
Smart 16-fold Low-Side Switch
Features Product Summary
• Short Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• 16 bit Serial Data Input and Diagnostic
Output (2 bit/chan. acc. SPI Protocol)
• Direct Parallel Control of Eight channels
for PWM Applications
• Parallel Inputs High or Low Active Programmable
• General Fault Flag
• Low Quiescent Current
• Compatible with 3V Microcontrollers
• Electostatic discharge (ESD) Protection
Supply voltage VS 4.5 – 5.5V
Drain source clamping voltage VDS(AZ)max 60 V
On resistance RON 1-8 1.0 Ω
RON 10,11,14,15 0.35 Ω
RON 9,12,13,16 0.3 Ω
Output current (Channel 1-8) ID(NOM) 0.5 A
(Channel 9-16) ID(NOM) 1 A
• μC Compatible Power Switch for 12 V and 24 V Applications
• Switch for Automotive and Industrial System
• Solenoids, Relays and Resistive Loads
• Robotic Controls
General description
16-fold Low-Side Switch (8 x 1.3 Ω, 4 x 0.4 Ω, 4 x 0.35 Ω) in Smart Power Technology (SPT) with a
Serial Peripheral Interface (SPI) and 16 open drain DMOS output stages. The TLE 6240 GP is protected
by embedded protection functions and designed for automotive and industrial applications. The
output stages are controlled via SPI Interface. Additionally 8 channels can be controlled direct in parallel
for PWM applications. Therefore the TLE 6240 GP is particularly suitable for engine management
and powertrain systems, safety and body applications.
Functional Description
The TLE 6240 GP is an 16-fold low-side power switch which provides a serial peripheral interface
(SPI) to control the 16 power DMOS switches, and diagnostic feedback. The power
transistors are protected against short to VBB, overload, overtemperature and against overvoltage
by active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic
output (SO).
Circuit Description
Power Transistor Protection Functions7)
Each of the 16 output stages has its own zener clamp, which causes a voltage limitation at the
power transistor when solenoid loads are switched off. The outputs are provided with a current
limitation set to a minimum of 1 A for channels 1 to 8 and 3 A for channels 9 to16.
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shutdown
with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6240 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the μC and vice
versa.
CS High to Low transition: - Diagnostic status information is transferred from the power
outputs into the shift register.
- Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits.
CS Low to High transition: - Transfer of SI bits from shift register into output buffers
.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6240 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information
is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consist of 16 bit, made up of one control byte and one data byte. The control
byte is used to program the device, to operate it in a certain mode as well as providing diagnostic
information (see page 14). The eight data bits contain the input information for the eight
channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic
data will appear at the SO pin following the rising edge of SCLK.
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Output Stage Control
The 16 outputs of the TLE 6240 GP can be controlled via serial interface. Additionally eight of
these 16 channels can alternatively be controlled in parallel (Channel 1to 4 and 9 to 12) for
PWM applications.
Parallel Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and respective
SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
and 9 to 12 are switched off. The PRG pin itself is internally pulled up when it is not connected.
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1to 4 and 9 to 12 are
high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 and 9 to 12 are
low active.
Serial Control of the Outputs: SPI protocol
Each output is independently controlled by an output latch and a common reset line, which
disables all outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A logic
high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it OFF.
CS must be low whilst shifting all the serial data into the device. A low-to-high transition of
CS transfers the serial data input bits to the output control buffer.
The 16 channels of the TLE 6240 GP are divided up into two parts for the control of the outputs
(ON, OFF) and the diagnosis information.
Channel 1 to 8:
Serial Input (SI) information consists of 16 bit. 8 bit contain the input driver information for
channel 1 to 8. The remaining 8 bits are used to program a certain operation mode.
Control Byte1: Operation mode and diagnosis select for channels 1 to 8
Data Byte1: ON/OFF information for channel 1 to 8
Serial Output (SO) data consists of 16 bit containing the diagnosis information for channels
1 to 8 with two bits per channel.
DIAG_1: Diagnosis data for channels 1 to 8.
Channel 9 to 16:
Control Byte2: Operation mode and diagnosis select for channels 9 to 16
Data Byte2: ON/OFF information for channel 9 to 16
DIAG_2: Diagnosis data for channels 9 to 16.
To drive all 16 channels and to get the complete diagnosis data of the TLE 6240 GP a two
step access has to be performed as follows:
First access:
SI command: Control Byte 1 programs the
operation mode of channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: Diagnosis information of
channel 1 to 8 or 9 to 16, depending on the
SI control word before.
SI command: Control Byte 1 programs the
operation mode of Channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: 16 bit diagnosis information
(two bit per channel) of channels 1 to 8
Detailed Description
As mentioned above, the serial input information consist of a control byte and a data byte. Via
the control byte, the specific mode of the device is programmable.
In the following section the different control bytes will be descriped. X used within the control
byte means:
X = L: Command is valid for channels 1 to 8
X = H: Command is valid for channels 9 to 16
1/6. LLLL XXXX - Diagnosis only
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per
channel) in accordance with Figure 1 (page 14). The data bits are ignored, so that the state of
the outputs are not influenced. This command is only active once unless the next control
command is again "Diagnosis only". Diagnostic information can be read out at any time with
no change of the switching conditions.
Example for two consecutive chip select cycles:
If the TLE 6240 GP is used as bare die in a hybrid application, it is necessary to know if proper
connections exist between the μC-port and parallel inputs. By entering ‘HHLL’ as the control
word, the first eight bits of the SO give the state of the parallel inputs, depending on the μC
signals. By comparing the IN-bits with the corresponding μC-port signal, the necessary connection
between the μC and the TLE 6240 GP can be verified - i.e. ‘read back of the inputs’.
The second 8-bits fed out at the serial output contains ‘1-bit’ fault information of the outputs (H
= no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the fault bit for
channel X.
To check the proper function of the serial interface the TLE 6240 GP provides a "SPI Echo
Function". By entering HLHL as control word, SI and SO are connected during the next CS
period. By comparing the bits clocked in with the serial output bits, the proper function of the
SPI interface can be verified. This internal loop is only closed once (for one CS period). The
“Echo Function” does not cause any internal processing of data and after the next CS signal
the SO data is “0” (all registers reset).
4/9. LLHH XXXX DDDDDDDD - OR operation, and ‘full diagnosis’
With LLHH LLLL as the control word, each of the input signals IN1...IN4 are 'OR'ed with the
corresponding SI data bits.
With LLHH HHHH as the control word, each of the input signals IN9...IN12 are 'OR'ed with the
corresponding SI data bits.
This OR operation enables the serial interface to switch the channel ON, even though the corresponding
parallel input might be in the off state.
SPI Priority for ON-State
Also parallel control of the outputs is possible without an SPI input.
The OR-function is the default Boolean operation if the device restarts after a Reset, or when
the supply voltage is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
5/10. HHHH XXXX DDDDDDDD - AND operation, and ‘full diagnosis’
With HHHH LLLL as the control word, each of the input signals IN1...IN4 are 'AND'ed with the
corresponding SI data bits.
With HHHH HHHH as the control word, each of the input signals IN9...IN12 are 'AND'ed with
the corresponding SI data bits.
The AND operation implies that the output can be switched off by the SPI data bit input, even
if the corresponding parallel input is in the ON state.
SPI Priority for OFF-state
This also implies that the serial input data bit can only switch the output channel ON if the corresponding
parallel input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
Diagnostics
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transition
as soon as an error occurs for any one of the sixteen channels. This fault indication can
be used to generate a μC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be
called after this fault indication. This saves processor time compared to a cyclic reading of the
SO information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. A new
error will over-write the old error report. Serial data out pin (SO) is in a high impedance state
when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially.
For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1.
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current
limitation gets active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V
(typ.). LH bit combination is set.
Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current
exceeds 100 μA, short to ground is detected and the LL bit combination is set.
A definite distinction between open load and short to ground is guaranteed by design.
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 150 μs to allow the outputs to
settle. Clock in the identical serial information once again - during this process the data coming
out at SO contains the bit combinations representing the diagnosis conditions as described
in figure 1.
Reset of the Diagnosis Register
The diagnosis register is reset after reading the diagnosis data (after the falling CS edge).
This is done for channels 1-8 and channels 9-16 separately depending on the previous command.
By means of the control byte it is possible either to:
a) control the outputs according to the data byte, as well as being able to read the
diagnostic information (two bits per channel)
or b) purely get diagnostic information without changing the state of the outputs
or c) read back the parallel inputs plus a simple diagnosis (one bit per channel)
or d) SPI "Echo Function" as a diagnosis of proper SPI function
a) Serial Control of Outputs
• LLHHLLLL LHLHHLLL
Control Byte Data Byte
SI information: OR-operation valid for channels 1 to 8.
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle.
• LLHHHHHH LHLHHLLL
Control Byte Data Byte
SI information: OR-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle.
• HHHHLLLL LHLHHLLL
Control Byte Data Byte
SI information: AND-operation valid for channels 1 to 8
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle.
• HHHHHHHH LHLHHLLL
Control Byte Data Byte
SI information: AND-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle.
b) Diagnosis Only
• LLLLLLLL XXXXXXXX
Control Byte Data Byte
SI information: Full diagnosis for channels 1 to 8. No change of output states.
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle.
• LLLLHHHH XXXXXXXX
Control Byte Data Byte
SI information: Full diagnosis for channels 9 to 16. No change of output states.
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle.
c) Read back of parallel inputs plus simple diagnosis
• HHLLLLLL XXXXXXXX
Control Byte Data Byte
SI information: No change of the output states. Read back of parallel inputs and 1 bit diag
nosis for channels 1 to 8.
SO:State of eight inputs plus 1 bit diagnosis for channel 1 to 8 during next chip select cycle.
• HHLLHHHH XXXXXXXX
Control Byte Data Byte
SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis
for channels 9 to 16.
SO: State of eight inputs plus 1 bit diagnosis for channel 9 to 16 during next chip select cycle.
d) SPI Echo function
• HLHLLLLL XXXXXXXX
Control Byte Data Byte
SI information: Echo function of SPI interface. No change of the output states.
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an
internal connection for this cycle
• HLHLHHHH XXXXXXXX
Control Byte Data Byte
SI information: Echo function of SPI interface. No change of the output states.
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an
internal connection for this cycle
Parallel SPI Configuration
Engine Management Application
TLE 6240 GP in combination with TLE 6230 GP (octal switch) for relays and general purpose loads
and TLE 6220 GP to drive the injector valves. This arrangement covers the numerous loads to be
driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled
direct in parallel for PWM applications.
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Old 20th December 2011, 09:41 AM   #5
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Hi pantiejun, I've merged your two threads. The vendors bazaar forum allows one thread per vendor. If you would like me to rename the thread title please hit the report post button (little red triangle with a line in it in the bottom left) and let me know what you would like it renamed to.

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Old 21st December 2011, 01:57 AM   #6
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Quote:
Originally Posted by wintermute View Post
Hi pantiejun, I've merged your two threads. The vendors bazaar forum allows one thread per vendor. If you would like me to rename the thread title please hit the report post button (little red triangle with a line in it in the bottom left) and let me know what you would like it renamed to.

If you wish to have more than one thread you can pay for a commercial forum.
My English is not very good:D
I wish to have more than one thread,How much should I pay?
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Old 4th January 2012, 07:57 AM   #7
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Default 2sb798 datasheet

2sb798 datasheet
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product details:
UPA1478H datasheet pdf,UPA1478H supplier,UPA1478H price,UPA1478H picture at UTSOURCE
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SILICON TRANSISTOR
2SB798
PNP SILICON EPITAXIAL TRANSISTOR POWER MINI MOLD
DESCRIPTION
The 2SB798 is designed for audio frequency power amplifier application, especially in Hybrid Integrated Circuits.
FEATURES
• World Standard Miniature Package
SOT—89
• Low Collector Saturation Voltage
VCE(sat) <—0.4 V (1c —1.0 A, 1B —--100 mA)
Excellent DC Current Gain Linearity
hFE = 100 TYP. (VCE —1.0 V, IC —1.0 A)
• Complements to NPN type 2SD999
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C) Maximum Voltages and Currents
Collector to Base Voltage VCBO Collector to Emitter Voltage VCEO Emitter to Base Voltage VESO Collector Current (DC)
Collector Current (Pulse)
Name: 2SB798-DM
Material of transistor: Si
Polarity: pnp
Maximum collector power dissipation (Pc): 2W
Maximum collector-base voltage (Ucb): 30V
Maximum collector-emitter voltage (Uce): 30V
Maximum emitter-base voltage (Ueb): 5V
Maximum collector current (Ic max): 1A
Maximum junction temperature (Tj): 160°C
Transition frequency (ft): 55MHz
Collector capacitance (Cc), Pf: 36
Forward current transfer ratio (hFE), min/max: 90T
Manufacturer of 2SB798-DM transistor: NEC
Package of 2SB798-DM transistor: SP0
Application of 2SB798-DM transistor: Medium Power, General Purpose
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Old 4th January 2012, 07:59 AM   #8
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Default 2sb798 dk

2sb798 dk
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product details:
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SILICON TRANSISTOR
2SB798
PNP SILICON EPITAXIAL TRANSISTOR POWER MINI MOLD
DESCRIPTION
The 2SB798 is designed for audio frequency power amplifier application, especially in Hybrid Integrated Circuits.
FEATURES
• World Standard Miniature Package
SOT—89
• Low Collector Saturation Voltage
VCE(sat) <—0.4 V (1c —1.0 A, 1B —--100 mA)
Excellent DC Current Gain Linearity
hFE = 100 TYP. (VCE —1.0 V, IC —1.0 A)
• Complements to NPN type 2SD999
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C) Maximum Voltages and Currents
Collector to Base Voltage VCBO Collector to Emitter Voltage VCEO Emitter to Base Voltage VESO Collector Current (DC)
Collector Current (Pulse)
1. Emitter
2. Collector
3. Base
Maximum Power Dissipation
Total Power Dissipation
at 25 °C Ambient Temperature
Maximum Temperatures
Junction Temperature
Storage Temperature Range
*3 10 ms, Duty Cycle 50 %
**When mounted on ceramic substrate of 16cm2 xO.7 mm
Document Name Document No.
NEC semiconductor device reliability/quality control system. TEl-i 202
Quality grade on NEC semiconductor devices. IE I-i 209
Semiconductor device mounting technology manual. IE I-i 207
Semiconductor device package manual. IE I-i 213
Guide to quality assurance for semiconductor devices. MEI-1202
Semiconductor selection guide. MF-1134
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use “Standard” quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
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Old 4th January 2012, 08:31 AM   #9
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I wish to have more than one thread,How much should I pay?
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Old 9th January 2012, 07:54 AM   #10
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Default Is Good or 2n5089 2N5088 Good?

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product details:
2N5088 datasheet pdf,2N5088 supplier,2N5088 price,2N5088 picture at UTSOURCE
If you want to buy more electronic components please visit:Buy Electronic components,Ic,Module,Transistor at UTSOURCE
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Amplifier Transistors
NPN Silicon
1. R JA is measured with the device soldered into a typical printed circuit board.
2. Pulse Test: Pulse Width 300 is, Duty Cycle 2.0%.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a sit uation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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