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Old 10th February 2012, 08:29 AM   #1981
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Quote:
Originally Posted by mr_push_pull View Post
no report after 9 hours...
now is there a possibility that all NCORE owners are abducted by aliens? it would explain a lot of things.
Time zones go a long way too.
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Old 10th February 2012, 08:35 AM   #1982
Julf is offline Julf  Europe
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Quote:
Originally Posted by mr_push_pull View Post
no report after 9 hours...
now is there a possibility that all NCORE owners are abducted by aliens? it would explain a lot of things.
No, I think that that cyanide capsule overvoltage protection circuit might have something to do with it...
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Old 10th February 2012, 08:40 AM   #1983
PHEONIX is offline PHEONIX  Australia
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Quote:
Originally Posted by Bruno Putzeys View Post

>>edit: I also worry about the SRC on the ESS not being defeatable (if it is the same one I tested 4 years ago it's not that great) but it becomes transparent if you lock all clocks together. The filters are programmable. But I wish they'd made just the back end available directly. Anyhow, if you look at some of the older and cheaper DAC chips, there's some serious performance to be had as well. Just look at the plots in the AD1955 data sheets (and imagine it's made with the rather ramshackle application circuit from the same data sheet and that they actually measure the whole signal instead of just the distortion residual).
Hello Bruno

Sorry to bore with a question on the ESS dac but you mention that the dac becomes transparent only when all the clocks lock together. What do you mean by this , should the upsampling rate be a multiple of the incoming rate when using the SRC in the chip or are you referring to the PCM filter roll off characteristics.

From their white paper, (Technical Details of the Sabre Audio DAC)

The Sabre DAC rate converter has two advantages compared to the
poly-phase filter approach and is described in great detail in
the pending patent. Firstly the rate conversion is unlimited
allowing the Sabre to always achieve a conversion into its .
exceptionally high clock rate (as much as 40Mhz) from as
little as 4Khz in one step; and secondly, the process is
essentially perfect to the bit level the output DNR exceeds
175dB and the THD is correspondingly high.



Regards
Arthur
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Old 10th February 2012, 08:40 AM   #1984
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Quote:
Originally Posted by Julf View Post
No, I think that that cyanide capsule overvoltage protection circuit might have something to do with it...
I think it's only legal to install those after the same customer sends us a fully working module back for repairs twice, and then only after they ask whether the faston tab marked "GND" on the UcD module was supposed to go to mains earth.

(It happened last week. Your suggestion of cyanide capsules has been duly noted)
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Last edited by Bruno Putzeys; 10th February 2012 at 08:47 AM.
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Old 10th February 2012, 08:47 AM   #1985
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@Arthur I think it would take us off topic to discuss in detail. ESS's claims regarding the SRC pertain to the actual interpolation process. They have done an absolutely splendid job there. The thing that causes problems is the ratio estimator (the bit that works out exactly what sampling time to interpolate). The bandwidth is too high which lets through time quantization errors. The circuit samples the incoming clock signal using its reference clock. This results in the addition of jitter with a peak-to-peak value of one reference clock period (e.g. 25ns for a 40MHz reference clock). Next the number of ref clock periods in one input clock cycle are counted and this constantly changing number is fed into a low-pass filter which outputs a cleaned-up version of the ratio between the reference and input clocks. This ratio is then used to space the "virtual resampling points" calculated by the interpolator. Of course the low pass filter doesn't output pure DC. The spectrum of the counter output consists of mix products between the two clocks. The filter can only attenuate those. The attenuated spectrum shows up as close-in FM sidebands exactly like jitter. DNR and THD measurements ignore those. The SRC successfully removes high-frequency jitter, thus guaranteeing good SNR, but it adds low-frequency phase modulation of the signal that wasn't even present in the input clock. All SRC's do this but the bandwidth of the low-pass filter determines whether this is an issue or not.

The attached two measurements were made on a standalone test chip for the ESS SRC which was never issued as a product, but the actual SRC did go on to be used in the Sabre DAC.
Attached Images
File Type: gif Slide97.GIF (18.0 KB, 630 views)
File Type: gif Slide98.GIF (22.2 KB, 614 views)
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Last edited by Bruno Putzeys; 10th February 2012 at 09:07 AM.
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Old 10th February 2012, 09:20 AM   #1986
ChrisPa is offline ChrisPa  United Kingdom
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Bruno

any feedback/update on the 'connecting a charged SMPS600 to an nc400' posts that appeared earlier in the thread?

I'd like to follow a modular approach to the cases which would mean and interconnect between psu and amp modules - but I won't do this if I may run into accidental problems with disconnection

Thanks
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Old 10th February 2012, 09:44 AM   #1987
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Yes. It's not a simple retrofit unfortunately. All dangerous connection sequences involve either or both of the Vaux rails being connected alongside with one of the high voltage rails and no ground. I can see my way clear of modifying the design for this, but modifying existing units looks difficult, at least if it's to be done in a tidy manner. The closest thing I can think of would be a pair of unidirectional TVS diodes from the two Vaux pins to ground - if they survive having the SMPS output caps being discharged across them.

I think the wisest thing for users who really must power up the smps without the amplifier attached is to discharge the smps after doing so.
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Old 10th February 2012, 10:14 AM   #1988
ChrisPa is offline ChrisPa  United Kingdom
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Quote:
Originally Posted by Bruno Putzeys View Post
I can see my way clear of modifying the design for this
Does that mean you're intending a future iteration of the modules with this modification in place?
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Old 10th February 2012, 10:34 AM   #1989
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That's the plan because making stuff foolproof trumps warning people every time.
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Old 10th February 2012, 10:44 AM   #1990
ChrisPa is offline ChrisPa  United Kingdom
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Quote:
Originally Posted by Bruno Putzeys View Post
That's the plan because making stuff foolproof trumps warning people every time.
Thank you

Any idea when that might hit your production batches?
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