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New FIFO buffer for RPI/SBCs
New FIFO buffer for RPI/SBCs
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Old 17th August 2016, 10:15 AM   #21
cdsgames is offline cdsgames  Canada
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Are the i2s signals on same pins ?
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Old 17th August 2016, 10:40 AM   #22
cdsgames is offline cdsgames  Canada
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I checked for Odroidc2...unfortunately it has a different i2s output.
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Old 17th August 2016, 02:54 PM   #23
sckramer is offline sckramer  United States
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Is this to be sandwiched between a pi & any Dac hat? To give better i2s to the Dac's PLL?

What about the Hat's that reclock already like Hifiberry Dac+ PRO & Digi+, and the pi2design prototype SPDIF board, would it be redundant?
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Last edited by sckramer; 17th August 2016 at 02:57 PM.
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Old 17th August 2016, 03:22 PM   #24
cdsgames is offline cdsgames  Canada
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Hi ,

yes the reclocker is between RPI and DAC.What it does is to buffer the DATA in memory and then reclocks i2s (outside FPGA) for the lowest jitter possible . We used an oscilloscope with a 2ps jitter floor and we have a reading of 3.081ps (rms) after buffer ..so very close to jitter floor, we will update this.We are using original NDK oscillators that are fed using pi filter and LDOs for a really clean power supply.

Now DAC+ pro has 2 xtals and operates in master mode. Its a good unit but definitely jitter wont be at the same (low) level.

In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
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Old 17th August 2016, 03:48 PM   #25
clivem is offline clivem  United Kingdom
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Originally Posted by cdsgames View Post
In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
Are you exposing MCLK as well as BCLK, LRCLK, DATA?

Sent you a PM about testing a board.
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Old 17th August 2016, 04:12 PM   #26
sckramer is offline sckramer  United States
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Quote:
Originally Posted by cdsgames View Post
Hi ,

yes the reclocker is between RPI and DAC.What it does is to buffer the DATA in memory and then reclocks i2s (outside FPGA) for the lowest jitter possible . We used an oscilloscope with a 2ps jitter floor and we have a reading of 3.081ps (rms) after buffer ..so very close to jitter floor, we will update this.We are using original NDK oscillators that are fed using pi filter and LDOs for a really clean power supply.

Now DAC+ pro has 2 xtals and operates in master mode. Its a good unit but definitely jitter wont be at the same (low) level.

In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
Hi cdsgames,

This is exciting stuff, can you stack reclocking boards on your board, give it a better source, or at least let it work transparently to try it out?

I'll link some threads from SBAF... a bunch of us are discussing, testing a prototype spdif board that's fairly advanced with it's power and clocking (it's a 4-layer board, pi ground filtering, many separate LDO's etc)
(and I'll link back to here... sure they will be interested.)

Also have been using piZERO, digi+, dac+pro, LDO -- to get the most out of it.

I'd def. be interested in a test board!

Thanks!
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Last edited by sckramer; 17th August 2016 at 04:16 PM.
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Old 17th August 2016, 04:15 PM   #27
cdsgames is offline cdsgames  Canada
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yeap we are exposing all. Send me a pm

Last edited by cdsgames; 17th August 2016 at 04:18 PM.
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Old 17th August 2016, 04:53 PM   #28
sckramer is offline sckramer  United States
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@cdsgames

Just FYI if you'd like to skim thru these quick, I'll just drop you in the middle somewhere

(My username is Scott Kramer there)

Link: SBAF pi digi+

Michael Kelly designed & built that spdif board (still just prototype) he has a few out testing.

Link: SBAF advanced digital hat
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Last edited by sckramer; 17th August 2016 at 04:58 PM.
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Old 17th August 2016, 05:24 PM   #29
cdsgames is offline cdsgames  Canada
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Originally Posted by sckramer View Post
Hi cdsgames,

This is exciting stuff, can you stack reclocking boards on your board, give it a better source, or at least let it work transparently to try it out?

Thanks!
Staking multiple reclocker wont improve anything...the clocks are discarded in the FPGA and a new clock its provided. Basically source has no value on i2s (our board) output
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Old 17th August 2016, 05:31 PM   #30
sckramer is offline sckramer  United States
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Quote:
Originally Posted by cdsgames View Post
Staking multiple reclocker wont improve anything...the clocks are discarded in the FPGA and a new clock its provided. Basically source has no value on i2s (our board) output
No, No I meant existing reclocking (maybe thats the wrong term, master mode) Dac's like the D+PRO, will they work...
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