I look forward to see your 100 page manual for your DAC
My DAC is DAC not a system so the manual will be small. Only the custom protocol we have used, since it will work with our FIFO Lite only.
The manual of the FIFO Lite instead will be a large manual with all the functions provided including the software to configure the device.
In the meantime you can take a look at the manuals I have already published to get an idea.
Here is my setup. Dont bother with the resample settings. I am doing the upsample in SOX.
(Think it sounds a bit better but that is me. Would probably fail bigtime in blind listening test
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No, you need to add leading or trailing (RJ, verses LJ and I2S) zeros to fill in the missing bits. You can look at the I2S data with a scope to see if volumio is adding zeros as it should it this case. There will be no high level data bits at one end of an LRCK frame, 16-bits of data and the rest zeros.
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Adding zeros is basically just padding the bitstream. If you do this with your 16-bit source it is still 100% the same data, not upsampled or anything. Perhaps not native 16-bit, but if it was supported the same operation would have happened in hardware.
Anyway. It will do nothing to the data. Just a matter of compatibility.
When byte shifting is used, it makes no formal difference whether it is done in the software or in the hardware. The question is only, which of the two variants becomes noticeable in (audible?) jitter. I personally avoid generating loads (e.g. in C/C++ RAM player command line code) if possible. There is also the software induced jitter.
But here it is anyway inevitable to decide for a variant. This also has nothing to do with the DAM specifically.
But here it is anyway inevitable to decide for a variant. This also has nothing to do with the DAM specifically.
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No manipulation in the digital domain of the payload ("the music") add jitter. Period. Why? Because the sample rate, i.e. the time, is implied. It is just samples that are subject to manipulation, not any clock. Clocks has time jitter. There is no clock present as you manipulate a say 16 bit word. Only calculation errors (rounding, truncation etc) occurs here. Jitter is only a problem where data and clock meet - and its the clock that has jitter - not the data. But as data is turned to music by using the clock... well, You figure it out
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No manipulation in the digital domain of the payload ("the music") add jitter. Period. Why? Because the sample rate, i.e. the time, is implied. It is just samples that are subject to manipulation, not any clock. Clocks has time jitter. There is no clock present as you manipulate a say 16 bit word. Only calculation errors (rounding, truncation etc) occurs here. Jitter is only a problem where data and clock meet - and its the clock that has jitter - not the data. But as data is turned to music by using the clock... well, You figure it out
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When you generate software-load, you generate hardware load at the same time. In extreme cases, this can even lead to crashes on a PC. It is always good to try to understand the sum of all events.
Yes - but it has noting to do with jitter. What you describe above will in its absolutely worst case, generate an under-run - that is loss of data. When a sample should have been available, it wasn't... Blipp...blopp..
But again.. thats not jitter. "Jitter" is not a collective name for "computer problem"... ;-)
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But again.. thats not jitter. "Jitter" is not a collective name for "computer problem"... ;-)
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I'm not sure the DAM was not affected by the source bit clock.
The ladder of the DAM1021 changes on the LRCK generated inside the FPGA dividing down the master clock from the Si514.
The master clock from the Si514 is continuously adjusted tracking the bit clock of the source (I believe).
Finally the LRCK, the most crucial signal for this kind of DAC, follows the bit clock of the source.
Anyway I know how add trailing zeros and I also know I can check the output from Volumio with an oscilloscope (since I'm designing FIFOs and DACs), but I expected the DAM was fully compliant with I2S protocol.
So does anyone know how have I to set Volumio to get the DAM working without resampling (simply adding trailing zeros)?
The ladder of the DAM1021 changes on the LRCK generated inside the FPGA dividing down the master clock from the Si514.
The master clock from the Si514 is continuously adjusted tracking the bit clock of the source (I believe).
Finally the LRCK, the most crucial signal for this kind of DAC, follows the bit clock of the source.
Anyway I know how add trailing zeros and I also know I can check the output from Volumio with an oscilloscope (since I'm designing FIFOs and DACs), but I expected the DAM was fully compliant with I2S protocol.
So does anyone know how have I to set Volumio to get the DAM working without resampling (simply adding trailing zeros)?
No idea, but you could simply convert the audio files you use for testing to 24 bit, couldn't you?