This is such a wrong approach to life. I understand people are different, but it is hard to digest good enough approach. Why not 32? Striving for higher goals should be preference. If the design gives that option without sacrifices in other areas so why not. It will hurt you if it measures better? Are you trying to manufacture 10,000 items so cost of each resistor will make the cost impact?
First, my belated appreciation and congratulations to Soren for a unique offering made available and affordable to a wide diy audience.
The way it is currently configured, the dominant jitter contribution is when the clock is divided in the FPGA. Whatever you do would be insignificant compared to the added jitter in the FPGA (which is in the order of 10s psec RMS (100s psec pp)) -based on what I can gather from the datasheets). Even the jitter added by the shift registers are in the psec range.
It's been a while, busy with day job and preparing for production. First, no, I haven't listened to it yet, know I should be there now. But I expect to finish up firmware while boards are being made....
Way off topic noise, please post thing like that elsewhere.
Answer to questions:
The plan is to supply boards without leaded connectors mounted, then you can those between wires or your favorite connectors. Holes will be 0.1" pitch, I will supply loose Molex/AMP MTA100 style headers.
It can't, but also don't need to. The Sign Magnitude DAC you can view as a sliding window DAC, great no matter the music level.
Actually only the FPGA 1.2V core voltage is SMPS, rest are linear ones, low noise as needed, designed to be feed directly from a single transformer.
See my next post.
Keep an eye on initial post for updates. I will make a priority list based on post here and PM's.
First batch do seems to be gone, hopefully there are enough in second batch for all who expressed interest here. And I will then keep making boards as long as they sell.
Actually I do plan to support DSD, all there is needed seems to be a little bit processing and a digital low pass filter. But not in first firmware release.
Way off topic noise, please post thing like that elsewhere.
Answer to questions:
The plan is to supply boards without leaded connectors mounted, then you can those between wires or your favorite connectors. Holes will be 0.1" pitch, I will supply loose Molex/AMP MTA100 style headers.
It can't, but also don't need to. The Sign Magnitude DAC you can view as a sliding window DAC, great no matter the music level.
Actually only the FPGA 1.2V core voltage is SMPS, rest are linear ones, low noise as needed, designed to be feed directly from a single transformer.
See my next post.
Keep an eye on initial post for updates. I will make a priority list based on post here and PM's.
First batch do seems to be gone, hopefully there are enough in second batch for all who expressed interest here. And I will then keep making boards as long as they sell.
Actually I do plan to support DSD, all there is needed seems to be a little bit processing and a digital low pass filter. But not in first firmware release.
The "Femto Clock" seems to be a marketing term for a Si570.... I don't do in marketing terms, but have designed my DAC for great total performance, having focused on getting all details right, but not overdoing anything not needed, as some do just for marketing purpose....
The Si570 is not that much more expensive, but the problem is power.... The Si514 is spec'ed at max 23 mA, the Si598 and Si570 at max 120 mA. And as their power is supplied from a linear regulator that could be a problem.... I also believe the Si514 with 0.8 pS RMS jitter is more than good enough, as other points out, there are probably more jitter in the digital logic, even as I have kept the logic path as short as possible.
External clock will not be supported as it will kill my FIFO, I need to be able to control the frequency digitally. I can't use a fixed clock and let a large FIFO take up the slack, as I also want low latency. I also believe the onboard clock with short signal paths is better than any external "perfect" clock with longer signal paths....
I'm curious about this choice.. DAC Ref voltages are highly critical - why SMPS here and linear for the rest?
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Jitter measured with an integration bandwidth from 12 kHz to 20 MHz tells about nothing for digital audio devices.
The right test should be integrating from 10 Hz to 1 kHz, or better from 1 Hz to 1 kHz.
With such this measurement, you'll discover a jitter of several ps, maybe several tens of ps. Not a big surprise if the FPGA jitter contribution will result lower than the intrinsic jitter of the Silicon Labs XO.
I'll love to see a phase noise plot for the clock managers in an FPGA to compare...
