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USB to I2S 384Khz - DSD Converter

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R

RayCtech

Member
Joined 2007
themystical said:
Perhaps deeper, better defined bass is perceived by me as less bass.
There probably are noise issues (in the electronic measurement sense) in my system as I use a lot of valves including in the output stage of the DAC
Yes running with a 80MHz clock. Not yet tried synchronous but probably worth exploring.
As a matter of interest, which quantizer setting gives you the best subjective fidelity. Does this align with 6bT apparently giving the best theoretical SNR and THD? What filter settings do you use?
Click to expand...

In general the higher the quantizer bit depth the better the fidelity.
True mode must be used.

Filters with highest bandwidth or no filters if possible..
 
C

charly chile

Member
Joined 2011
I like this Discussion, looks like we are summarizing lots of experiences and info spread around many different websites.

Another questions:

-Anyone did percive sound quality improvement eliminating USB power supplay and using an internal DAC 3.3V source?
- I am using Buffalo III with amanero and I am looking at the Buffalo manuals to figure out if I have a 3.3V source that I can use to feed amanero, but not sure if it's worth it.
- What about those I2C isolator chips?

Cheers
 
T

themystical

Member
Joined 2006
RayCtech said:
Lower jitter = deeper bass and better defined bass.
Thus I expect your system may have jitter or noise issues.
Click to expand...

I found this statement by Dustin Forman, the chip designer very illuminating with regard to the DPLL Bandwidth setting.(although not made in the specific context of the Sabre DAC chip)
http://www.diyaudio.com/forums/digital-source/89435-jitter-blocking-2.html#post1047747
The issue appears not to be purely about "unlocks" but also about "reading" all of the data it receives. In this context, the "Lowest" setting although providing a full lock might not be "best" setting and there may be some data loss occuring. This may also explain my perceived better bass and 'not thin sounding' at higher DPLL bandwidth settings. The "best" setting ultimately depends on your source....and getting the balance between jitter rejection and "reading all of the data" right. Anybody know the algorithm used by ESS for determining the "Best" setting in their ES9018 chip?
 
G

glt

Member
Joined 2004
diyaudio.com/forums/showthread.php?s=&threadid=140669
themystical said:
I found this statement by Dustin Forman, the chip designer very illuminating with regard to the DPLL Bandwidth setting.(although not made in the specific context of the Sabre DAC chip)
http://www.diyaudio.com/forums/digital-source/89435-jitter-blocking-2.html#post1047747
The issue appears not to be purely about "unlocks" but also about "reading" all of the data it receives. In this context, the "Lowest" setting although providing a full lock might not be "best" setting and there may be some data loss occuring. This may also explain my perceived better bass and 'not thin sounding' at higher DPLL bandwidth settings. The "best" setting ultimately depends on your source....and getting the balance between jitter rejection and "reading all of the data" right. Anybody know the algorithm used by ESS for determining the "Best" setting in their ES9018 chip?
Click to expand...

From my own observations, it appears "Best" is near the high side of the scale. I think it is just a constant setting rather than an algorithm. Of course this is just based on observations.
 
T

themystical

Member
Joined 2006
glt said:
From my own observations, it appears "Best" is near the high side of the scale. I think it is just a constant setting rather than an algorithm. Of course this is just based on observations.
Click to expand...

My listening experience would suggest that although the Amanero interface locks at the lowest settings without any issues, higher settings are required for the Sabre to retrieve all of the data. Other guys running the Amanero interface into a Sabre chip could perhaps listen to "high side" settings and post some views?
I noticed that Dustin Forman's last post was in 2011 so I guess it is not possible to get a definitive response from ESS on this forum anymore?
 
R

regal

Member
Joined 2004
GOOD NEWS. The new intel chipset (8 series) for Haswell will have native USB2.0. I was afraid that they would go full USB 3.0 since USB 3.0 has native asynchrous mode making UAC2 and any 480mbs USB 2.0 drivers obsolete.

But the fact that intel is sticking with a native USB 2.0 we can be comfortable both on the Mac side and the PC side for many years. Anyone who has tried to run a 480bs USB interface from a USB3.0 port knows that it is NOT backwards compatible.
 
TNT

TNT

Member
Joined 2003
Paid Member
qusp said:
what IV stage are you using? just using DSD instead of i2s isnt going to somehow circumvent analogue stages that dont have offset. its more likely to be a glitch/transient caused by the overlapping of different samplerates. particularly given the ESS isnt playing native DSD, its converted to 6 bit blocks internally in the dac, not acting as a 1bit analogue filter.
Click to expand...

qusp, do you know of a 1bit analogue filter solution available today.. i.e. tru to the DSD concept?

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