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Old 3rd July 2018, 05:45 PM   #161
Russ White is offline Russ White  United States
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It is still - actually synced - because the DPLL is ultimately driven by the master clock - it is just superfluous and a heavyweight process that does not need to exist with a synced clock.
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Old 3rd July 2018, 05:48 PM   #162
Russ White is offline Russ White  United States
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This is why when running sync clock without the "pure sync" firmware it is often best to open up the DPLL - so that it basically does nothing but freewheel. With a jittery async source this would be bad - because it would let the jitter through - with a clean source already synced to the master clock it has no ill effects.
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Old 3rd July 2018, 06:47 PM   #163
shadowlight is offline shadowlight  United States
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Hello,
I am interested in leveraging the solution to pull I2S signal from DSC 2.5.2 and run HQPlayer NAA on Beagle Bone Black but I am not 100% sure what is needed.

Please correct if my list is not accurate:
Hermes-BBB Isolator Module, Cronus Re-clocking Module, 45.1584MHz Rhea Module and 49.152MHz Rhea Module. Do I also need the 22/24 clocks? When would I need the 22/24 clocks v/s 45/49 clocks?
What would I need from power perspective?

TIA
@BrianDonegan and @Russ White,

Is my list correct?
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Old 3rd July 2018, 07:32 PM   #164
barrows is offline barrows
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Goto, I do not really agree with regarding running sync clocking with the ESS DACs: if the masterclock and bit clock arrive at the DAC in sync, then the DPLL does nothing: that is, the DPLL is active, but it does not have to do anything, and makes no changes. Now if the masterclcok and bit clock arrive at the DAC slightly out of sync, then the DPLL will make a slight adjustment. But this mode is entirely different from running a 100 MHz masterclock which has no relation to the bit clock at all, then the DPLL is fully active all the time.
I hear significant differences in both 9018 and 9038 chips running with a synchronous clock vs async as well.

But: back to the issues at hand. So frustrating here that with async DAC operation Amanero firmware 1099c runs well with native DSD 256 on linux, and sync DAC mode does not lock at all. Masterclock lines are checked and fine, so I am at a loss at to what could be the problem. OE firmware on the Amanero ran fine in sync mode as well, of course limited to DSD 128 via DoP, as it does not work for native DSD on linux.

Again the question: is anyone successful at running Amanero/Cronus, with Amanero firmware v: 1099c, Slave for CPLD, in sync mode (masterclock from Cronus to DAC) and 45.1584 masterclock? Or does anyone have any ideas why this might not work?
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Old 3rd July 2018, 07:56 PM   #165
BrianDonegan is offline BrianDonegan  United States
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Introducing the Hermes-Amanero
Since you are using only one clock, can you verify that the clock select signal is high?
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Old 3rd July 2018, 07:59 PM   #166
barrows is offline barrows
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Default Hi...

Quote:
Originally Posted by BrianDonegan View Post
Since you are using only one clock, can you verify that the clock select signal is high?
Brian, I went ahead and mounted both XOs on the Cronus to make sure the single clock approach was not causing any issues. I figured this was a simple thing to do to eliminate variables.
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Old 6th July 2018, 09:16 PM   #167
barrows is offline barrows
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Default Update...

Quote:
Originally Posted by BrianDonegan View Post
Since you are using only one clock, can you verify that the clock select signal is high?
OK, as a check, I switched out the 45.1584 (Crystek/Rhea) with 22.5792 I had around, and then set the divided to 1:1. Voila, Sync mode working (also with just single clock and a u.fl jumping the two clock positions).

With this clock rate I only get to DSD 128, and PCM 24/96 so I guess I need to try a new 45.1584 XO...
Before I go this route, of getting the new clock and thinking that is the problem, is there anything which could be damaged on the Cronus board to explain this problem? I would think the divider has to be OK, as the Amanero has operated fine all the time, perhaps the mux? Maybe the clock signal was clean enough for Amanero to operate but not for the 9038 to lock on it.
Still seems weird, But my guess is the next step is trying a new 45.1584 XO.
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Old 7th July 2018, 02:38 AM   #168
Russ White is offline Russ White  United States
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Yes, clock replacement would be my next move.

Cheers!
Russ
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Old 8th July 2018, 11:22 AM   #169
twluke is offline twluke  Japan
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Introducing the Hermes-Amanero
Quote:
Originally Posted by barrows View Post
OK, as a check, I switched out the 45.1584 (Crystek/Rhea) with 22.5792 I had around, and then set the divided to 1:1. Voila, Sync mode working (also with just single clock and a u.fl jumping the two clock positions).
I think this is a good choice. I've been checking the feasibility of the syncmode (Puresync by Russ) firmware for sharing the clocks on the remote Cronus connected to either Herms-BBB or Hermes-Amanero using Teleporter. The MCLK at the receiver end of TP is directly connected to the clock input of the DAC (a 9028 pro in this case). The results were quite successful. There was no problems in playing DSD512 from the remote Hermes-BBB (via HQ player) as expected.

What was more remarkable was that the Hermes-Amanero with 22/24 clocks on the Cronus could play DSD256 (DoP) through both of HQ player and Audirvana Plus running on My Macbook with this syncmode beta firmware despite remotely connected via the Teleporter. One more thing. This condition becomes easily lost when SW1:1 is set to normal (on). I think this benefit is owing to 128fs but will not talk about it here . BTW, the firmware of Amanero is 2004be. Also you don't need to be persistent with using uFL cables. My experiments were all done with wire cables.

Get the beta firmware before renewal of the clocks.
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Old 8th July 2018, 01:07 PM   #170
Russ White is offline Russ White  United States
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Hi twluke,

There is nothing surprising there.

In puresync (128fs) mode (puresync firmware) it would be expected to work.

Remember the DoP decoding is happening at the amanero. The Hermes/Cronus/DAC are only seeing DSD.

So for DSD256 you only need:

((2.8224Mhz * 4) / 64) * 128 = 22.5792Mhz

Remember in 128fs mode the mck only need be evenly divisible by 128fs - so: MCK % 128fs = 0 = valid master clock.

DSD played in PureSync mode will also work exactly the same (measured) for DSD64 and DSD128 using that same 22.5792Mhz clock. To reach DSD512 you will need the 45 Mhz clock and PureSync. For DSD1024 - you need 90Mhz and PureSync (as well as a source that can actually do it).

Cheers
Russ
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Last edited by Russ White; 8th July 2018 at 01:10 PM.
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