Buffalo III - SE

[miero]

When we assume that Buffalo III crystal is good enough already, so why not use it as reference clock?

For such use we need to be able generate clock for 44.1/58/96/... kHz stream and export it as SPDIF clock/Masterclock/Wordclock, so it could be used to as clock reference in the source device, e.g. in the sound card.

Could it work?

[roender]

Originally Posted by miero

When we assume that Buffalo III crystal is good enough already, so why not use it as reference clock?

For such use we need to be able generate clock for 44.1/58/96/... kHz stream and export it as SPDIF clock/Masterclock/Wordclock, so it could be used to as clock reference in the source device, e.g. in the sound card.

Could it work?

Do you know a method to generate 24.5760Mhz and 22.5792Mhz from BIII 100Mhz clock and in the same time preserving his phase noise for the mentioned frequencies?
I do not know any other than using a PLL which don't cont because will add a lot of jitter

[miero]

OK, I don't know. But do we really need to have the precise clock in the source? I guess the information loss during transport might be lower when the source transmits signal with the known jitter, i.e. same as is in DAC. The jitter on the transport would be there, but then it would be eliminated in the ASRC.

In other words I think it might improve quality of data transport, not the timing.

[Russ White]

Miero, it is an interesting idea. One cool thing is that even if the PLL or clock generator had some error, it would be an error that would be in synch with the master clock... And since at the DAC the incoming signal would be resynced to the original master clock... Well the results could be interesting.

Here is the cool thing. if one wanted to they could do it, by using the UFL connector on the B-III SE as an output, instead of an input. Then you have something to feed a PLL/Clock generator

Don't let anyone discourage you from trying it if you have the motivation.

[roender]

Originally Posted by miero

OK, I don't know. But do we really need to have the precise clock in the source? I guess the information loss during transport might be lower when the source transmits signal with the known jitter, i.e. same as is in DAC. The jitter on the transport would be there, but then it would be eliminated in the ASRC.

In other words I think it might improve quality of data transport, not the timing.

I don't want any ASRC .... It is my subjective choice.
In this case is paramount to have a very good phase noise clock in DAC and source as well. Clock must be close to the DAC and divided accordingly with the source needs.

[BrianDonegan]

The conversation is drifting into a generalized discussion on DAC clocking methodology, which would be better discussed elsewhere on the forums...

[BrianDonegan]

Had some time for building. Here is the Buffalo-IIIse with optional u.fl connectors.

The connector for EXT_MCK will be pre-installed standard. The u.fl connectors for I2S and S/PDIF will be available as an uninstalled option (they are not that hard to solder). As usual, terminal blocks are included in the kits.

The IP_S pads in the foreground control the input switching (S/PDIF or I2S) via a simple switch or digital logic.

[RollE2k]

Brian: The switching, will it be simlar to the 4-spdif board that you short to pads of the IP_S, and if "programmed" with external controller, what kind of command would you need to send to "switch", just a 5v(to two bits in different orders?)

[roender]

Hi Brian,

As far as I know CCHD-950 dosen't have chip enable (tristate output) option. Which XO is used in this version of Buffalo DAC?
There's an option for BIII-SE without XO?

Kind regards,
Mihai

[glt]

Originally Posted by BrianDonegan

Had some time for building. Here is the Buffalo-IIIse with optional u.fl connectors.

The connector for EXT_MCK will be pre-installed standard. The u.fl connectors for I2S and S/PDIF will be available as an uninstalled option (they are not that hard to solder). As usual, terminal blocks are included in the kits.

The IP_S pads in the foreground control the input switching (S/PDIF or I2S) via a simple switch or digital logic.

Brian,

What are Ic4, Ic5?