BII 80Mhz still going strong...
Was able to play 352.8K tracks without any noise. Critical parameters seem good I2S wiring arrangement, FIR filter set to slow, Quantizer at 8bit true differential.
The only issue is during silence (pause, gap or stop) where instead of silence, I get a loud hiss with very peculiar characteristics:
The level and tone of this hissing sound changes with the volume setting with some settings giving more volume than other settings but not related to the amount of volume attenuation. In addition, FIR sharp filter results in a louder noise than the slow filter. The quantizer bit depth also changes the amount of noise coming from the DAC. The IIR filter and the notch delay don't seem to have any effect.
Any hints as to what is going? I know the upgrade to 100Mhz clock was to resolve some of these issues, but when playing music the 80MHz clock doesn't seem to cause any problems.
Are there any secret register I can use?
Was able to play 352.8K tracks without any noise. Critical parameters seem good I2S wiring arrangement, FIR filter set to slow, Quantizer at 8bit true differential.
The only issue is during silence (pause, gap or stop) where instead of silence, I get a loud hiss with very peculiar characteristics:
The level and tone of this hissing sound changes with the volume setting with some settings giving more volume than other settings but not related to the amount of volume attenuation. In addition, FIR sharp filter results in a louder noise than the slow filter. The quantizer bit depth also changes the amount of noise coming from the DAC. The IIR filter and the notch delay don't seem to have any effect.
Any hints as to what is going? I know the upgrade to 100Mhz clock was to resolve some of these issues, but when playing music the 80MHz clock doesn't seem to cause any problems.
Are there any secret register I can use?
The only issue is during silence (pause, gap or stop) where instead of silence, I get a loud hiss with very peculiar characteristics:
Any hints as to what is going? I know the upgrade to 100Mhz clock was to resolve some of these issues, but when playing music the 80MHz clock doesn't seem to cause any problems.
Are there any secret register I can use?
I had met same probrem when I was trying to play 352.8k files
on my 80mhz Buffalo II. I couldn't solve this and felt clock upgrading makes it far easier...
Thanks for the replies.
(The following only relates to NOT playing music with 352.8Khz material: during stop, pause or gap between songs, and only to the 80MHz part)
Russ: 9 bit Pseudo differential gives a higher pitch hiss
wktk_smile: yes, upgrade will solve the problem, but for now I don't want to touch the board; it is so well made
I did further experiments:
If I turn the volume digitally (at the application, OS or driver) to zero, then the noise appears. So somehow it can't handle continuous zero data.
If I turn the volume digitally near zero, then clicks/crackling will appear...
(The following only relates to NOT playing music with 352.8Khz material: during stop, pause or gap between songs, and only to the 80MHz part)
Russ: 9 bit Pseudo differential gives a higher pitch hiss
wktk_smile: yes, upgrade will solve the problem, but for now I don't want to touch the board; it is so well made
I did further experiments:
If I turn the volume digitally (at the application, OS or driver) to zero, then the noise appears. So somehow it can't handle continuous zero data.
If I turn the volume digitally near zero, then clicks/crackling will appear...
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glt
One thing you could do is remove the ferrite that powers the on-board clock and try passing in the master clock from your source. Running a synchronous clock makes it easier to lock on to really high sample rates, but it come at the cost of moving the clock reference to one that may not be as low jitter.
But since you are experimenting it might be fun to try.
One thing you could do is remove the ferrite that powers the on-board clock and try passing in the master clock from your source. Running a synchronous clock makes it easier to lock on to really high sample rates, but it come at the cost of moving the clock reference to one that may not be as low jitter.
But since you are experimenting it might be fun to try.
I absolutely agree.
But considering that considerable amount of effort has been invested in the ASRC:
- Patented technology
- Use of an ultra low phase noise Crystek clock next to the DAC. The clock is an integral part of Buffalo probably laid out for minimal perturbation
- Dedicated power supply for the Clock
Bypassing it just doesn't feel right
But considering that considerable amount of effort has been invested in the ASRC:
- Patented technology
- Use of an ultra low phase noise Crystek clock next to the DAC. The clock is an integral part of Buffalo probably laid out for minimal perturbation
- Dedicated power supply for the Clock
Bypassing it just doesn't feel right
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ASRC...
GLT: there are those who feel an ASRC sounds unnatural. Wavelength Audio uses the ESS chip in synchronous clocking mode for this reason. I have not listened to a synchronously clocked B-II or B-III yet, but I would like to try it and see...
As far as clocking goes, the CCHD clock is pretty nice...of course if one provides an I2S source with an equally good MC, and short, well implemented clock transmission lines, all should be good.
I would like to see a USB-I2S source with CCHD (or similar spec) clocks, and dedicated shunts for the clocks' supplies...hint, hint...
GLT: there are those who feel an ASRC sounds unnatural. Wavelength Audio uses the ESS chip in synchronous clocking mode for this reason. I have not listened to a synchronously clocked B-II or B-III yet, but I would like to try it and see...
As far as clocking goes, the CCHD clock is pretty nice...of course if one provides an I2S source with an equally good MC, and short, well implemented clock transmission lines, all should be good.
I would like to see a USB-I2S source with CCHD (or similar spec) clocks, and dedicated shunts for the clocks' supplies...hint, hint...
There is no "Synchronous clock mode" really You are either using a synchronous clock or your not. This actually only effects the very first part of the digital input and OSF.
I am not against using a synchronous clock. But I would never buy into the hype that anything else sounds "unnatural". Because I know better.
You are either using a synchronous clock or your not. This actually only effects the very first part of the digital input and OSF.I am not against using a synchronous clock. But I would never buy into the hype that anything else sounds "unnatural". Because I know better.
Yeah...
If you have a DDS generated clock it is likely best to stick with the onboard CCHD as MC, agreed then. I have also noted that some reputable commercial DAC designers, who previously did not like the sound of hardware based ASRC implementations have actually embraced the ASRC as implemented in the ESS chips: most notably Daniel Weiss. The ESS approach to ASRC does seem to sound better than many others (TI for instance).
I still wonder what the ESS 9018 will sound like synchronously clocked with a ultra low jitter/phase noise I2S MC source... Gotta try at some point.
barrows,
Absolutely agree.
But since my source clock is generated by the FPGA, there is no way I'm trading that with the CCHD clock.
BTW, I am not too fond of winged Buffaloes (hence I am trying hard to stick with the BII)
If you have a DDS generated clock it is likely best to stick with the onboard CCHD as MC, agreed then. I have also noted that some reputable commercial DAC designers, who previously did not like the sound of hardware based ASRC implementations have actually embraced the ASRC as implemented in the ESS chips: most notably Daniel Weiss. The ESS approach to ASRC does seem to sound better than many others (TI for instance).
I still wonder what the ESS 9018 will sound like synchronously clocked with a ultra low jitter/phase noise I2S MC source... Gotta try at some point.
I would say it sounds absolutely awesome.
I have tried it. But the clock does need to be very good. Keep in mind. Things are still internally relocked. Just at an exact multiple.
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They are still oversampling.
I see, in "normal mode". That means the clock must be >192 FS
Suppose the source clock is 192fs. For 352.8KHz material that means 67.733 MHz. That is still below the 80 MHz of the current clock
Suppose the source clock is 256fs. For 352.8KHz material that means 90.316 MHz. That should be high enough to fix the noise problem
However, I seriously doubt my source is generating that frequency for the MCK.
OK, I think I was confusing "synchronous" with OSF bypass (which requires a much lower frequency MCK -only >24fs)
Passing 100Mhz clocks with simple wiring is probably not a diy type of thing
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