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Old 15th December 2010, 06:10 PM   #1041
labjr is offline labjr  United States
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Quote:
Originally Posted by Russ White View Post
It has the ability to generate a clock yes, but it is *only* that generated clock that is ill and in the case of the ESS DAC it is not used at all. In any way.

SPDIF does not even really "have a clock", but you can derive a clock from it. That is the heart of the issue where standard receivers are used.

No clock extraction (which usually requires some type of PLL) is done at all in the case of ESS method.

The data is just data which is queued, and gets stuffed into a buffer. Much the same way that asynchronous USB works.

SPDIF once you are not running through a PLL to obtain a clock is just like any other 1 wire protocol.

Seems like you are taking ESS's marketing literally about their little trick for S/PDIF. Now matter what they call it, or how they do it, it's still a reclocking scheme. Bottom line is the data still has to be lined up and converted by the DAC at exact timing intervals to prevent jitter. And since S/PDIF data flow can't be controlled, the clock has to be adjusted to prevent overflow or underrun of the data. This creates more jitter.
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Old 15th December 2010, 06:16 PM   #1042
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Marketing? I couldn't care less about that. I don't have to rely on what they say in public I have material I can actually look at. Including a couple patents.

Some of what I know is covered by my NDA or I could explain a bit better. But it is exactly as I described. I will leave it at that.
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Old 15th December 2010, 09:19 PM   #1043
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Default Well...

No matter how "immune" the ESS 9018 is to incoming jitter, it is clearly not entirely immune. Any change I make to a transport, or SPDIF cable is clearly audible in the output of my B-II. Just like it always has been with any DAC of my experience, notwithstanding all claims of "jitter immunity" made by many manufacturers.
It seems the more resolving the DAC/System, the more clear it becomes to me that jitter is audible, even at very, very low levels.
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Old 15th December 2010, 09:40 PM   #1044
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Quote:
Originally Posted by Russ White View Post
It has the ability to generate a clock yes, but it is *only* that generated clock that is ill and in the case of the ESS DAC it is not used at all. In any way.

SPDIF does not even really "have a clock", but you can derive a clock from it. That is the heart of the issue where standard receivers are used.

No clock extraction (which usually requires some type of PLL) is done at all in the case of ESS method.

The data is just data which is queued, and gets stuffed into a buffer. Much the same way that asynchronous USB works.

SPDIF once you are not running through a PLL to obtain a clock is just like any other 1 wire protocol.
And how can it differentiate zeros from ones without knowing the pattern that separates bits (clock)? Before storing it on the buffer, it needs to know exactly each zero and one in the exact order for storing it, until the DAC needs that data.
How does it manage to do that?



Quote:
Originally Posted by Russ White View Post
Then the noise is likely not from your wiring. More likely from the source.

The DPLL is really finicky about phase noise. You can widen the DPLL window but then you are passing in some of that phase noise down stream.
Will the TPA Transport be a good solution noise-wise? I am sure you guys are developing a quite state of the art device, so keep it going!

Regards,
Regi
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Old 15th December 2010, 09:51 PM   #1045
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Russ has made some very confident sounding statements about the forthcoming USB interface board. I trust that he is working very hard to make this interface a state of the art solution, with very little compromise in its design.
I am very much looking forward to trying the new interface when it is available, as I expect it will raise the performance of the B-II up another notch. (and I am already experiencing great computer audio perfromance with my B-II, via a Wavelink USB-SPDIF converter).
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Old 15th December 2010, 09:59 PM   #1046
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I think its wrong to assume that any perceived differences you might hear between sources are all about jitter. That is really rejecting quite a lot else that could be going on. You need to consider much more here. There are a lot of places that things can be mucked up or enhanced depending on your tastes that have nothing at all to do with jitter.

And please don't mistake what I am saying for something its not. I never said any DAC was completely immune to any particular effect.
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Last edited by Russ White; 15th December 2010 at 10:04 PM.
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Old 15th December 2010, 10:02 PM   #1047
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Quote:
Originally Posted by regiregi22 View Post
And how can it differentiate zeros from ones without knowing the pattern that separates bits (clock)? Before storing it on the buffer, it needs to know exactly each zero and one in the exact order for storing it, until the DAC needs that data.
How does it manage to do that? i
I will give you 2 clues.

1) Bi-phase marking make differentiating 0's and 1's easy without any "bit clock".
2) Search for some comments by Dustin on this forum. He actually did a great bit of explaining how its done.
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Last edited by Russ White; 15th December 2010 at 11:10 PM.
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Old 15th December 2010, 10:11 PM   #1048
labjr is offline labjr  United States
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This can be deduced with common sense. With Async USB or Firewire the DAC can stop the dataflow. With S/PDIF you can't. So whether you strip the clock out of the data or not, the data keeps coming at the speed of the S/PDIF clock and this is why S/PDIF will always have more jitter.

From what I've heard, as good as the ESS DAC may be, even Dustin Forman, the Sabre DAC designer, believes this.
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Old 15th December 2010, 10:23 PM   #1049
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Default Yeah...

Quote:
Originally Posted by Russ White View Post
I think its wrong to assume that any perceived differences you might hear between sources are all about jitter. That is really rejecting quite a lot else that could be going on. You need to consider much more here. There are a lot of places that things can be mucked up or enhanced depending on your tastes that have nothing at all to do with jitter.

And please don't mistake what I am saying for something its not. I never said any DAC was completely immune to any particular effect.
I sort of know what you are saying, but, it is hard to really understand what else there might be affecting the sound when we have "bit perfect" data, and jitter: what else is there in the digital realm, this is what confuses me. Once we get into the DAC chip, and its oversampling/filters, etc, there are all kinds of effects to the sound, but just in data transfer, it is hard to understand what is going on beyond the bits and jitter.
I know you do not ascribe to the "jitter immune" rhetoric.
If you have a moment, I would love to hear some ideas from you as to what other factors might effect the sonics of data transfer to the DAC chip besides the bits and jitter. Are you thinking there are artifacts (unrelated to the data) in the digital signal that will be converted into noise/distortion products by the DAC?
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Old 15th December 2010, 10:33 PM   #1050
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I think there is no accounting for perception in its many wonderful and mysterious forms.

But lets talk about decoding for a minute. You don't have to control the SPDIF flow to accurately receive it and then quantify it. You are thinking far to linearly.

I have been playing with a very similar technique to receive SPDIF using XMOS. If you have a fast clock and a few samples worth of buffer, it is not a problem at all.
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