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Twisted Pear Audio - Buffalo32S (ES9018 DAC)

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Improving power supply for Buffalo32S

I have been experimenting with a different power supplies for B32S.
The standard was two LCBPS (+/-15V) for the analog sections and one LCDPS (+5V) for the digital section. I first changed the 5V supply for the digital section to a 5V JSR03 from sjostromaudio. No big change.
Next I build four JSR modules (15V negative, positive, left and right) for the analog section(s) of B32S. This gave a very noticeable improvement. I'm not good in describing the changes in sound but I would say that it is more lively and airy. I have tried going back to the LCBPS, but now the sound seems a bit dark and relaxed. I guess similar (or even better) improvement would/will be observed with the Placid supply that I'm under the impression TPA will release soon.
I have been wondering why the change of supply for the digital section was without much effect and my sense of logic suggest two possibilities:
1) There is little to improve. It is already just about as good as it gets.
2) There is no improvement because the weak link is the on-board regulators.
I see 3 onboard LT1763. Two of these are 3.3V and one is variable and set to 1.22V as far as I can measure. Out of curiosity, with a faint idea of tinkering, I'm trying to figure out what these regs are powering. One 3.3V reg connects to both the DAC chip as well as the PIC. The 1.22V connects to the DAC chip. I can only guess that the second 3.3V reg is powering the clock. Has anybody looked at this in more detail and tried any modding?
Thanks,
Nic
 
Nic, forgive my ignorance but what are JSR modules.

Alan

Jung Super Regulators. They are linear series pass type regulators.

Placid, which should be at my door today or tomorrow is a shunt regulator.

LCBPS is a very solid power supply that we designed mostly for practicality and bang for the buck value. Placid is designed for low noise and low output impedance as well as excellent line and load regulation. The trade off is that Placid is a bigger more complex module.

As for the on-board supplies on the Bufallo32S they were carefully designed. Feel free to fiddle with them. But they do precisely what they are designed to do already. :)

There are three digital supplies.

1) 1.22V which runs the chip core and provides the gate supply for the level shifters into the modulator.

2) 3.3V which runs DVCC on the chip.

3) 3.3V for the ultra low phase noise clock.

Cheers!
Russ
 
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Joined 2009
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Hi Russ,
The LCBPS and LCDPS are indeed great bang for the buck! I'm using these supplies in several projects and I once calculated that the kit price is inferior to what I would have to spend on the components here in Europe (+ the PCBs from you). I even power the JSR's with these supplies! I just can't have enough of these around.

I know that the regulators for the digital section are doing their work very well. I can hear that! I'm just wondering if it can be done better.
Maybe the psychological effect of spending 100$+ on upgrading these with discrete shunt regs would be greater than the real difference in sound!

Would you happen to know the approximate power load on these three regs?

Looking forward to Placid, Ballsie Lite and AC1 :spin:
Nic
 
Yes within the filter within the DAC itself. :)

Oh ho. You can load the filter? That sounds like fun - and useful too. I've never been a huge fan of half-band filters for anti-aliasing.

By the way, what's the actual sampling rate of the DAC? I know it has an ASRC before it, but I'd like to get my DSP as close to the native frequency as possible. Getting dither out of the audible range is rather easier if the sampling rate is well above 48 kHz.
 
I know, but I am not at liberty to say because of my NDA.

That's OK, I figured out how to get that information: generate a square wave at different sampling rates and see what it looks like at the DAC outputs. The Gibbs ringing will tell me all I need to know to design the dither.

Speaking of I2S, the B32s layout drawing shows D1, D2, and DCLK beside the SPDIF input. I haven't seen how these map onto I2S SCLK, WS, SD. DCLK is probably SCLK, but the others are unclear. Did I miss something?
 
That's OK, I figured out how to get that information: generate a square wave at different sampling rates and see what it looks like at the DAC outputs. The Gibbs ringing will tell me all I need to know to design the dither.

Speaking of I2S, the B32s layout drawing shows D1, D2, and DCLK beside the SPDIF input. I haven't seen how these map onto I2S SCLK, WS, SD. DCLK is probably SCLK, but the others are unclear. Did I miss something?

D1 is the word clock
D2 is Data
DCLK is the bit clock.

Cheers!
Russ
 
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