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#1 |
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diyAudio Member
Join Date: May 2007
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MODERATORS NOTE:
This is a thread split off from the "ESS Sabre Reference DAC (8 Channel)" thread here: ESS Sabre Reference DAC (8-channel) because it contains posts referring directly to the Buffalo DAC boards which are produced by Twisted Pair. Discussion regarding these products by Twisted Pair should take place on this new thread here: Variac ![]() END MODERATOR'S NOTE __________________________________________________ ____ Hi, all Buffalo/IVY users ![]() I've been testing Buffalo for the last days and I've noticed one interesting thing. Has anyone compared balanced/SE output vs. SE output is connected to + and GND of balanced output pins (of course, sound level will be halved in this configuration)? I did and difference is huge, especially in soundstage and consequently in detail. And this is in favor in the second configuration! ![]() Matej |
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#2 | |
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diyAudio Member
Join Date: Apr 2002
Location: *
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Quote:
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#3 |
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diyAudio Member
Join Date: May 2007
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On IVY connect + and G (of balanced output pins) to RCA
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#4 | |
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Jackass of All Trades
diyAudio Member
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Quote:
I plan on sending out a revised component pack this week to those of you from the first run. We just want to be solid on the values.
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Abiding Diax's Rake |
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#5 |
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diyAudio Member
Join Date: Jan 2002
Location: Cheltenham
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Hello Russ, are you planning to ship the Buffalo as 9 bit then?
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#6 | |
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Jackass of All Trades
diyAudio Member
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Quote:
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Abiding Diax's Rake |
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#7 | |
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diyAudio Member
Join Date: May 2007
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Quote:
))Can you also check balanced output vs. my suggestion? I've tried balanced and it does not play harmony to me (but I do have cheap balanced cables). Cheers, Matej |
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#8 | ||
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Jackass of All Trades
diyAudio Member
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Quote:
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The current plan for the updated components is this (may still change slightly in the next day or so): -> R1-R4: 178R (as originally shipped) -> R5-R8: 357R (as originally shipped) -> R9-R12: 2K (replaces 1K shipped, to fix SE gain) -> C1, 2, 7, 8: Omit -> Add 220pF MKP across input terminal block pins (+ to GND and - to GND, both channels) -> Add 22-220pF MKP across R13-R16 Possibly replacement PIC with change to 9-bit quantizer I will post pics of the cap additions as well.
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Abiding Diax's Rake |
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#9 |
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diyAudio Member
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Can I ask whether Bufflo take AES? I know it takes SPDIF but Is the board capable of direct AES wiring without additional component?
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#10 |
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diyAudio Member
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Some notes about how the Buffalo/IVY measurements so far.
Dustin has graciously measured the Buffalow/IVY in a pretty basic configurations prior to my latest round of design changes (based on his feedback). IVY on its own was measuring a very solid 133db DNR and -117db THD+N. This is actually a bit better than I had expected. ![]() The Buffalo/Ivy combo was doing 122db DNR in the configuration Dustin was using (the limiting factor here being HF noise from the DAC) and -117db THD+N. Still excellent, but I know it can do even better. This is the reason for the slight circuit change(input LPF). The combo has not been tested yet in the new configuration. But I ave good reason to believe we will get better DNR. By way of example, my PCM1794 board has much less HF energy coming out of that DAC. This is very apparent in A/B tests. using similarly configured IVYs. Bottom line is the ESS chip just needs more attention to clean up the analog signal. Dustin only has so much time, so he has not tested the latest changes I have tried. Maybe at some point. If he can't do it I will see if some of my other friends can. In the end I don't want to end up getting tied up just chasing numbers. It sounds excellent with the current setup, and the that's the main point. I think the numbers will be improved also. We know based on the limited measurements I have so far that the combo measures well, and I expect its even better now. The main thing we learned on the IVY is that the THS4131 does not like a pure capacitive load, so you cannot use a feedback cap of >240pf or so without adding some series resistance. With the filtering on the front end you actually should not need any cap there at all. Hopefully this sheds some light on the design process and will help others designing output stages for the Sabre chip. ![]() Cheers! Russ
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