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Old 6th September 2006, 08:48 PM   #51
Mad_K is offline Mad_K  Norway
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Very enlightening reading
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Old 6th September 2006, 09:37 PM   #52
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Sheldon,

Thanks for checking my math. Yes, capacitance values would be somewhat different at a Vgs value of something other than zero, but that chart was all I had to go on. The “jitter” values were so large that a little error in calculation just won’t change matters much.

I think it was convenient to measure these capacitance values at 1 MHz, since impedances might be get too high at lower frequencies to measure accurately. I doubt the capacitance values would be much different at lower frequencies. At higher frequencies lead inductances start to factor in so they probably thought that 1MHz was a low enough frequency to allow ignoring the inductances. And a lot of test equipment measures at 1 MHz as a standard.

I don’t see anything special happening at 3 volts, since the curve smoothly rises as you move left across the whole chart. If you limited the voltage swing, it certainly would reduce the distortion, the same as with almost any other distortion mechanism, but then you have a lower power amplifier. On another thread where a MOSFET was a driver and not the final stage, it was noted that when you bias these high voltage devices to closer to their maximum spec for Vds, the Crss drops in value and becomes more constant. But here a 200 Volt supply with 2 amps flowing wouldn’t work!

Despite good intentions about including tubes, if one were insistent on using MOSFETs as in this amp, this is one case where I drive them with a low impedance solid-state source. Nelson Pass seems to have taken this road. You will notice that almost every node in his circuits is at a very low impedance. Even so, you will see rising distortion at higher frequencies in his test data, indicating that capacitance is starting to “weigh down” the amp stages.
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Old 6th September 2006, 10:22 PM   #53
MIKET is offline MIKET  United States
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Default Time to decide what we want

Design Goals:
1. Gain 20-40, this will alow a cd player to drive the MOSFET to full output.
2. Low output impedance. Wide Band performance.
3. Low parts count. We are using this to drive SEWA, otherwise would be wrong from a purist standpoint.
4. Output Swing 20V p-p minimum to assure we can get all 7 watts out of the MOSFET.
5. SE design no NFB.............thats my goal, but don't think it's unreasonable.

Those are my goals.......your thoughts
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Old 6th September 2006, 11:11 PM   #54
tinitus is offline tinitus  Europe
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Here are lots of info on hybrids

http://www.wdehaan.demon.nl/hybrid/index.html
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Old 7th September 2006, 04:48 AM   #55
Tyimo is offline Tyimo  Hungary
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Hi Dsavidsk!

Quote:
I use something similar for a DAC gain stage after a passive I/V.
Very nice preamp! Could you tell us the specs?
Gain, output voltage, etc?

Tyimo
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Old 7th September 2006, 09:23 AM   #56
Ryssen is offline Ryssen  Sweden
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If I use a E81L as a CF how do I know what the R out will be?
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Old 7th September 2006, 09:35 AM   #57
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Default Re: Time to decide what we want

Quote:
Originally posted by MIKET
Design Goals:
1. Gain 20-40, this will alow a cd player to drive the MOSFET to full output.
2. Low output impedance. Wide Band performance.
3. Low parts count. We are using this to drive SEWA, otherwise would be wrong from a purist standpoint.
4. Output Swing 20V p-p minimum to assure we can get all 7 watts out of the MOSFET.
5. SE design no NFB.............thats my goal, but don't think it's unreasonable.

Those are my goals.......your thoughts
Reasonable. I second
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Old 7th September 2006, 03:10 PM   #58
Sheldon is offline Sheldon  United States
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Quote:
Originally posted by Brian Beck
I don’t see anything special happening at 3 volts, since the curve smoothly rises as you move left across the whole chart. If you limited the voltage swing, it certainly would reduce the distortion, the same as with almost any other distortion mechanism, but then you have a lower power amplifier. On another thread where a MOSFET was a driver and not the final stage, it was noted that when you bias these high voltage devices to closer to their maximum spec for Vds, the Crss drops in value and becomes more constant. But here a 200 Volt supply with 2 amps flowing wouldn’t work!
Oops, my mistake. Misplaced a zero. The steep uptick takes place around 30 volts for this FET. I have been looking at STB24F10 and STP20N20, where the Crss is pretty low and begins a steep rise arounng 3-5Volts. Sorry for the confusion. So for the Ir transistor, the input limiting strategy for a low power amp would be completely useless. For my application, I'm looking at a reflected impedence of the tube stage to be about 2K and the voltage at the FET's to be about 45V. So the Crss would be below 50 or so, until Vds dropped below about 3-4V, for a corner frequency of about 160K.

Sorry for the slightly off topic excursion.

Sheldon
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Old 7th September 2006, 05:10 PM   #59
DougL is offline DougL  United States
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Quote:
1. Gain 20-40, this will alow a cd player to drive the MOSFET to full output.
My understanding of CD output levels are about 2 V RMS.
In my design notes, I assume a nominal 1 V RMS input, or about 3 V pp.

Given that, a minimum gain of 7 would give the 20V pp that is required.

I was doing a paper design inspired by your requirements:
CSS loaded ECC99 with an EDCOR 10k:600 interstage transformer parafead between Cathode and Plate (Anode).
Current tentatively set to about 10 Ma.

with a B+ of 240V, Plate Signal swing should be about 132 Vpp (6 Vpp input * mu 22), while output signal swing should be 1/4 of that, or about 33 Vpp. Output Z should be Rp/ 16, or 125 ohms.

Compromises:
Gain is a bit light for 1 Vrms, which "only" giving 16 Vpp.
The $12 EDCOR transformer is only good to 25 Vrms @ 30hz, which maxes out @ about 18 Vpp @ 30Hz
The 240V PS may be a culture shock for the intended audience.

I'll draw a schematic later today.
Any feedback welcome.

Doug
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Old 7th September 2006, 05:20 PM   #60
Zen Mod is offline Zen Mod  Serbia
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Quote:
Originally posted by DougL


My understanding of CD output levels are about 2 V RMS.
In my design notes, I assume a nominal 1 V RMS input, or about 3 V pp.

Given that, a minimum gain of 7 would give the 20V pp that is required.

I was doing a paper design inspired by your requirements:
CSS loaded ECC99 with an EDCOR 10k:600 interstage transformer parafead between Cathode and Plate (Anode).
Current tentatively set to about 10 Ma.

with a B+ of 240V, Plate Signal swing should be about 132 Vpp (6 Vpp input * mu 22), while output signal swing should be 1/4 of that, or about 33 Vpp. Output Z should be Rp/ 16, or 125 ohms.

Compromises:
Gain is a bit light for 1 Vrms, which "only" giving 16 Vpp.
The $12 EDCOR transformer is only good to 25 Vrms @ 30hz, which maxes out @ about 18 Vpp @ 30Hz
The 240V PS may be a culture shock for the intended audience.

I'll draw a schematic later today.
Any feedback welcome.

Doug

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