Tube Pre Amplifier for SEWA 7 Watt ClassA MOSFET

[Fuling]

You'd be bandwith limited to about 600KHz...

So we could get to 30kHz with 20kohm output impedance?

[Mad_K]

Teoretically, yes

[Ryssen]

Teoretically, yes

Wich means,for a pretty novice,no good ,or...
Trying do make up my mind wich way to go..

[Mad_K]

I would try to keep the source impedance below 5K (to keep 100KHz bandwith)

[Fuling]

I would aim for an even lower source impedance, preferably not more than a couple of hundred ohms.
In my experience powerful driver stages always sounds better than whimpy ones, even if both technically are capable of driving the load. This goes for both tube and mosfet output stages.

Just my two cents

[Brian Beck]

My 2 cents worth also:

You need much greater bandwidth in the gate driver than you might think to avoid distortion. Here’s why:

The driving resistance, whether it’s the plate resistance of a common-cathode stage or the cathode resistance of a CF, and the gate capacitance form a roll-off together at a pole frequency of 1/(2*pi*R*C). At that pole frequency, amplitude drops by 3dB and phase is shifted by 45 degrees. At one tenth of the pole frequency (perhaps down into the “audio band”), amplitude drops by only 0.043 dB and phase shift is -5.7 degrees.

So if the pole is set to 200KHz, as a convenient example, then if we look at the top of the audio band at 20KHz, the amplitude is down by only 0.043dB and the phase is retarded (“delayed”) by 5.7 degrees. That equates to 0.8 microsecond of “delay” at 20KHz. That doesn’t sound too scary.

So what?

In the case of the IRFP240, we need to worry primarily with Crss (= Cdg) which in the follower configuration is not amplified by the Miller effect happily. But it’s bad enough. (We’ll ignore the bootstrapped Cgs for simplicity). At the operating point of around 11 volts drain-to-source (Vds), Crss is about 350pF. To achieve a 200KHz roll-off (just for sake of example) we’d need to drive it with a resistance of no higher than about 2200 ohms, which is easily achievable with a decent triode’s plate. Is all well then? No, read on...

Vds can vary by almost +/- 10 volts from this operating point as it swings with signal. The problem is that Crss varies from about 200pF at Vds = 20 volts to about 1300pF at Vds = 1. This means that the RC time “constant” that determines the pole frequency and phase shift is not constant at all; it varies dramatically with signal voltages. This variation creates a phase intermodulation mechanism that defines, I believe, the difference between the sounds of MOSFETs and tubes. I believe that some people equate phase intermodulation with detail and etching, when it fact it’s false detail and distortion.

Taking the simple math one step further for this example (bear with me): As I said, when the output signal approaches the peak positive level, Crss approaches 1300pF. Driven by our hypothetical 2200 ohm driver, the pole frequency then drops from 200KHz to about 54KHz. Looking again at the amplitude and phase shift effects at 20KHz we see an amplitude drop of 0.55dB and a phase shift of -20.3 degrees. So the gain at 20 KHz actually CHANGES as the signal swings, from -0.043 dB to -0.55dB. And phase shift grows from -5.7 degrees to -20.3 degrees at 20KHz. When several frequencies are introduced into the amp at the same time (i.e. music) these signals will intermodulate with each other in both time and amplitude.

Converting that phase shift to time at 20 KHz, the high end of the audio band is delayed by an additional 2 microseconds as the signal swings positive (and by a lesser amount in the other direction too, which we’ll ignore). That’s 2,000 nanoseconds or 2,000,000 picoseconds. You can think of this as a kind of jitter. In the digital world, we’ve learned that the ear is exquisitely sensitive to jitter. We believe that jitter down into the hundreds of picoseconds may still be audible. Granted, not all jitter mechanisms are alike. But what we have in this example is a peak “jitter” of about 2,000,000 picoseconds. Across a lesser signal swing or at lower audio frequencies we might see “only” 2,000 to 20,000 picoseconds of jitter. That range is still orders of magnitude more than we would hope for.

Design implication: The MOSFET’s gate needs to be driven from a very, very low drive resistance to force the pole to a very high frequency where lingering phase shift in the audio band is reduced. At the very least, the gate deserves a CF driver using a high mu, high gm tube, and even that may not be enough. IMO, of course.

Edit: These numbers seem worse than even I would have predicted. I hope that someone will check my math and make sure that I didn't make a mistake. The message is still valid though, even if a decimal point is off by a space.

[lineup]

hi

first decision to be made
for preamp for SEWA amp
http://www.diyaudio.com/forums/attac...amp=1157451156

Should we use the existing power supply of SEWA
or
make a separate power supply for the tube pre amp

Both ways are surely possible.
But for best results I think tube should have its own supply
a bit higher voltage and not very much current TRAFO


what you say guys?

[Ryssen]

Alright then.. I will use a separate tarnsformer for a (180v)CF and try ECC86 for voltage tube.

[lineup]

Originally posted by Ryssen
Alright then.. I will use a separate transformer for a (180v)CF and try ECC86 for voltage tube.

no doubt this is best way for best performance of the tube

but what about this approch, used with good result



the link is http://www.customanalogue.com/diytub...lone/index.htm
as i told before in this topic

[Sheldon]

Originally posted by Brian Beck
My 2 cents worth also:

You need much greater bandwidth in the gate driver than you might think to avoid distortion. Here’s why:

The driving resistance, whether it’s the plate resistance of a common-cathode stage or the cathode resistance of a CF, and the gate capacitance form a roll-off together at a pole frequency of 1/(2*pi*R*C). At that pole frequency, amplitude drops by 3dB and phase is shifted by 45 degrees. At one tenth of the pole frequency (perhaps down into the “audio band”), amplitude drops by only 0.043 dB and phase shift is -5.7 degrees.

So if the pole is set to 200KHz, as a convenient example, then if we look at the top of the audio band at 20KHz, the amplitude is down by only 0.043dB and the phase is retarded (“delayed”) by 5.7 degrees. That equates to 0.8 microsecond of “delay” at 20KHz. That doesn’t sound too scary.

So what?

In the case of the IRFP240, we need to worry primarily with Crss (= Cdg) which in the follower configuration is not amplified by the Miller effect happily. But it’s bad enough. (We’ll ignore the bootstrapped Cgs for simplicity). At the operating point of around 11 volts drain-to-source (Vds), Crss is about 350pF. To achieve a 200KHz roll-off (just for sake of example) we’d need to drive it with a resistance of no higher than about 2200 ohms, which is easily achievable with a decent triode’s plate. Is all well then? No, read on...

Vds can vary by almost +/- 10 volts from this operating point as it swings with signal. The problem is that Crss varies from about 200pF at Vds = 20 volts to about 1300pF at Vds = 1. This means that the RC time “constant” that determines the pole frequency and phase shift is not constant at all; it varies dramatically with signal voltages. This variation creates a phase intermodulation mechanism that defines, I believe, the difference between the sounds of MOSFETs and tubes. I believe that some people equate phase intermodulation with detail and etching, when it fact it’s false detail and distortion.

Taking the simple math one step further for this example (bear with me): As I said, when the output signal approaches the peak positive level, Crss approaches 1300pF. Driven by our hypothetical 2200 ohm driver, the pole frequency then drops from 200KHz to about 54KHz. Looking again at the amplitude and phase shift effects at 20KHz we see an amplitude drop of 0.55dB and a phase shift of -20.3 degrees. So the gain at 20 KHz actually CHANGES as the signal swings, from -0.043 dB to -0.55dB. And phase shift grows from -5.7 degrees to -20.3 degrees at 20KHz. When several frequencies are introduced into the amp at the same time (i.e. music) these signals will intermodulate with each other in both time and amplitude.

Converting that phase shift to time at 20 KHz, the high end of the audio band is delayed by an additional 2 microseconds as the signal swings positive (and by a lesser amount in the other direction too, which we’ll ignore). That’s 2,000 nanoseconds or 2,000,000 picoseconds. You can think of this as a kind of jitter. In the digital world, we’ve learned that the ear is exquisitely sensitive to jitter. We believe that jitter down into the hundreds of picoseconds may still be audible. Granted, not all jitter mechanisms are alike. But what we have in this example is a peak “jitter” of about 2,000,000 picoseconds. Across a lesser signal swing or at lower audio frequencies we might see “only” 2,000 to 20,000 picoseconds of jitter. That range is still orders of magnitude more than we would hope for.

Design implication: The MOSFET’s gate needs to be driven from a very, very low drive resistance to force the pole to a very high frequency where lingering phase shift in the audio band is reduced. At the very least, the gate deserves a CF driver using a high mu, high gm tube, and even that may not be enough. IMO, of course.

Edit: These numbers seem worse than even I would have predicted. I hope that someone will check my math and make sure that I didn't make a mistake. The message is still valid though, even if a decimal point is off by a space.

Interesting analysis Brian. Your math seems correct. A couple of questions: The Crss figures are quoted at measurement conditions of f 1MHz and Vgs of 0. Do the figures change under conditions that would be typical for an audio amp? It looks like those Crss curves tend to take off around 3V or so. Couldn't one deal with the issue by considering that 3V level a kind of clipping point and design the driver to stay below it for standard input levels? This should be less of a limitation with stages driven by higher voltages. I'm looking at a different kind of mosfet output stage, so this is interesting to me.

Sheldon