Hybrid for Zobsky

[kenpeter]

Just thinking how to balance the output stage currents.
I want the MOSFET to "warm up" with the Tetrode and
keep all currents in balance. I've also put a shunt reg
for imaginary screen currents on the MOSFET side too.

I am aware much (the entire front end) is missing.
All far from a working simulation yet.

[kenpeter]

I wonder if its fair game to call C3 an "Ultrapath"?

[kenpeter]

Here's some Schade feedback, as Zob requested.

Yeah, I put it on the MOSFET, but the curve of lesser transconductance
is dominant here, and that would still be the Tetrode! So, we Schade
this Tetrode by returning partial feedback to its Cathode. Advantage
theoretically is a higher input impedance. But I don't know if thats an
actual advantage? if G1 benefits by being allowed to leak, that might
outweigh desire for a high input impedance. I may end up Schading
on the Tetrode side yet, or both...

I got to do some math or get this a little more simmable to adjust the
DC current leaking through R13 on the right side to match that leaked
by R4 on the left side.

-----


Hmmmm... Maybe if I Schade the Tetrode side to allow more grid leak?
I could feed the input signal to the MOSFET's gate instead... Yeah, that
might be the ticket. Think I can Schade and still keep input impedance
rather high. More redraw...

[kenpeter]

A few tweaks and re-arrangements...

I've realized MOSFET source voltage will always come up first,
so makes more sense for that end of our ultrapath be positive.

I'm also abusing MOSFET to drive the cathode of the Valve.
Means I have to raise the source voltage to have room for
our input signal to swing above current mirrored collectors.

MOSFET and bridging cap together make an Ultrapath.
Folded cascode ultrapath action also makes this MOSFET
behave as an anti-triode, doubling power in the process.

----

I am Schading this Tetrode for Triode behavior by way of
inductively coupled partial feedback to the grid. Schade's
original did this, so why not???

----

Don't start wiring anything yet. Its still not yet simmed.
Think at this point, we need to confirm how many Henries
on each winding of those 10WCXPP? And find us an 6AQ5
spice model, if a true 6P1P model is not available.

----

Aside from an anti-triode in the signal path, all other sand
here is performing constant current or shunt regulator duty.
Plausibly deniable as "outside the signal path".

You can ignore all the BJTs as-if they were not there for
purpose of understanding the signal path. That much I've
kept simple as possible.

[kenpeter]

Whoops... Shunt reg for screens need a rethink.
I've created amazingly poor PSRR by shunting
noise that would have gone to the screen onto
the input signal instead (and done so twice!).

If I return Q3 and Q4 collectors to GND instead,
there is no PSRR problem. But also no accounting
for screen current in the mirror below. This is all
fixable somehow, just need to think about it...

[smoking-amp]

Ken, to increase your available tools, there is another option available that can be used for anti-triode behavior.

For ideal class A P-P operation, the sum of the currents from the B+ would be constant. For real devices, the B+ current will vary due to distortion components. By putting a current sense resistor in the B+ line, one can pick off a feedback signal at the primary center tap. Using that as neg. feedback to both sides will try to maintain constant current (WE harmonic neutralizer, or common mode feedback). Feedback to one side only will make one side anti-triode to the other, uncorrected, side. (1/2 WE harmonic neutralizer). More toys to play with.

One might even consider positive feedback on one (other) side as well. Or frequency selective. Delayed maybe? .... Screen grids convenient for such feedbacks too, but less gain.

[kenpeter]

I could put bypass caps on R2 and R3, and return unused screen currents
there instead... But emitter bypasses would need pretty big caps, and the
bypass reduces collector impedance needed to keep sandy parts invisible.

Might just need to pre-regulate for PSRR first, then shunt screen to cathode
after the threat is gone. But I'm preferring to look for a low part count trick.

Any PSRR that makes it down the shunt regs to the twin tail will take the
low impedance source back up to B+, and surely will not cancel evenly by
the slightly higher impedance cathode path.

[kenpeter]

Ditched some parts that just weren't working out...

I am thinking less now of screen current as an "error"
at the cathode to be avoided. With Schading in effect,
its a parasitic triode cathode follower of no value seen
at the plate. But would add some output via ultrapath,
so not entirely useless. Half useless is certainly better
than entirely...

The main thing to worry is still the DC balance. But I
think will be good enough, if I can make the leakage
below the cathode into R4 similar to the average leak
at the screen. Will demand some tweaking to balance
out the leaks, but perhaps the price paid for simplicity.

I think my bias into the mirror at the bottom is wrong?
Will focus on fixing that area next. Where I was gonna
be tweaking anyway... Seems obvious that R9 must be
a far larger value than R2, else very little current will be
taking the path of the mirror with the added VBE drop.

My own fault for simulating entirely by imagination,
and not throwing a proper model at this Tetrode to see
what an actual calculation might have to say about it.

[kenpeter]

Firstly, I find the equivalent tetrode model
I needed was probably 6v6 all along. Sub
whatever MOSFET for the moment, not yet
trying for ultimate accuracy on that side.

Also not sure bout the transformer model,
I need to measure the seconday inductance
(the primary was beyond my meter's range)
and can probably compute the rest.

Right away we got some problems more
severe than weather we have chosen the
best representative .models.

I was perhaps mistaken to think screen
currents in the ultrapath could be turned
to our advantage? Screen current at the
Cathode makes the MOSFET ultrapath
current swing wider than our Tetrode.

The MOSFET bottoms out on zero mA
before Tetrode swing is fully realized.
else we have to bias the MOSFET side
higher, and we lose some DC balance.
Or perhaps add some fake plate current
in parallel with the Tetrode to restore
the balance.

Anyways, I am getting frustrated with
all the sandy clutter at the bottom,
and looking for more elegant ways to
enforce this balance. So far, nothing...
I'll keep hammering at it.

[kenpeter]

Originally Posted by smoking-amp

Ken, to increase your available tools, there is another option available that can be used for anti-triode behavior.

For ideal class A P-P operation, the sum of the currents from the B+ would be constant. For real devices, the B+ current will vary due to distortion components. By putting a current sense resistor in the B+ line, one can pick off a feedback signal at the primary center tap. Using that as neg. feedback to both sides will try to maintain constant current (WE harmonic neutralizer, or common mode feedback). Feedback to one side only will make one side anti-triode to the other, uncorrected, side. (1/2 WE harmonic neutralizer). More toys to play with.

One might even consider positive feedback on one (other) side as well. Or frequency selective. Delayed maybe? .... Screen grids convenient for such feedbacks too, but less gain.

B+ longneck presents problems too.

Anti-device and side of the transformer must dump all power ripple.
Both sides don't warm up and cool down together, nor does it force
equal DC when its done. I wish transformer had separate center taps,
all sorts of quadrature feedback schemes for dynamic shaping of bias
come to mind... Predictable square law crossing of Schottky diodes
would not place much feedback on Square law beam tetrodes, only
keep them in proper bias as they age. But that's a different day with
a different transformer. Today I have a 10W 5K CXPP to work with...
Have to fudge something with existing parts.