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Old 17th December 2011, 04:21 AM   #21
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Quote:
Originally Posted by siliconray View Post
The MOSFET has 1300pf Cg so it needs low output impedance to drive, especially when the freq is high. SRPP because the output impedance is low. I think the distortion is acceptable for a hybrid amp. I believe 50% of the distortion is cause by the mosfet. It's a design without global feedback.
CGS is negligible, for the source follows your gate. There is little energy
stored or released in such a capacitor. SRPP can drive it easily. Capacitor
that worries is CGD! Even though this value might seem small at first.

Miller can be terrible in a MOSFET. Because they conduct so well, we are
tempted to abuse them with low drain voltage. But take away bias that
makes drain capacitance so much less than source? Suddenly, your CGD
cap just got a whole lot larger!!! Worse case, might become a 50/50 split
with the source capacitance. And the effect is multiplied by any voltage
gain...

Keep 10V or more upon your drain, nothing bad is going to happen.
You don't have to worry 1300pF, so long as drain bais shoves most of
that problem to the source end of things, where it can do less harm.

Last edited by kenpeter; 17th December 2011 at 04:26 AM.
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Old 17th December 2011, 03:02 PM   #22
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Thanks Kenpeter. I'll redesign the circuit and simulate it with pspice. When the new PCB is fab out I'll send you one kit for testing, thanks for your help.
Quote:
Originally Posted by kenpeter View Post
Something like this....

Top MOSFET and voltage divider set voltage.
Bottom MOSFET and current sensors set the
current, and current balance.

The sum of currents sensed by R5 + R6 will
mate for equal and opposite class A currents.
With a fixed total that does not fight itself.
MOSFETs don't need to match, only R5 R6 do...

SRPP is not battling against collector Q1,
Collector is working in your favor this time...
BJT wont be driven to saturation nor cutoff.
Won't hear Q1 struggle to recover anymore.

Ferrite bead prevents possible oscillation.

M1 does not need a bootstrap. C1 provides
the ability for drive to briefly exceed the rail.
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Old 17th December 2011, 03:26 PM   #23
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Quote:
Originally Posted by kenpeter View Post
Keep 10V or more upon your drain, nothing bad is going to happen.
You don't have to worry 1300pF, so long as drain bais shoves most of
that problem to the source end of things, where it can do less harm.
Does that mean higher supply voltage will make the performance better? My testing result is: THD is 0.05% when Vp-p is 1V, but when Vp-p increased to 5V, THD raise to 0.27%. The supply is +-15V.
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Old 18th December 2011, 05:37 AM   #24
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MOSFETs switch exceptionally well at low drain voltages, just capacitance
won't stay put where you would like (nor expect) for low-volt linear purpose.
Hard to say a thing with gain won't oscillate, when you don't know from one
moment to the next, to which end of your capacitance might shift???

But your application is unity gain follower. Plenty of local feedback assures
the source voltage has little freedom to deviate. Miller cap trying to squirm
back and forth from source to drain end at low volts is a managable problem.

So long as you don't attempt to make voltage gain with your MOSFETs,
I think low voltage capacitance misbehavior can be adequately controlled.
Its a matter of brute force, unity gain follower conveniently provides...

Yes, higher supply voltage could make the cap behave better. But more
is never enough. Some fool will just crank up the volume, till drain bias
problems return. Gotta enforce your linearity, even in that worst case...

Last edited by kenpeter; 18th December 2011 at 05:57 AM.
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Old 20th December 2011, 09:09 AM   #25
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Default Redesign of circuit

Redisigned a new circuit, it's attached.

Did some simulation with LTspice for the MOSFET part of the hybrid amp. The previous circuit has -48dB 2nd harmonic while the new version has only -62dB, much less distortion. PCB will arrive on Friday, hope there's a better result. My target is <0.1% THD for the entire circuit.
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Last edited by siliconray; 20th December 2011 at 09:12 AM.
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Old 21st December 2011, 07:36 PM   #26
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Q3 needs to be PNP. BC560 perhaps?

And provide enough spread between through-holes
to slip a ferrite bead upon either its base or emitter.

Last edited by kenpeter; 21st December 2011 at 07:44 PM.
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Old 21st December 2011, 11:03 PM   #27
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opps..mistake, it shoud be bc560. Same PCB design :-)
Will add a bead
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Old 21st December 2011, 11:25 PM   #28
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If we assume both mosfet Sources follow the plate with near zero source impedance,
and 0.7V offset between them: We can compute 0.7V/0.4R = 1.75A quiescent current.
We can also compute the output impedance as 0.2R PAR 0.2R = 0.1R.
And the damping factor probably 8R / 0.1R = 80.

This might be slightly off if the source impedances aren't negligible, and I have not
done any calculations yet to determine the truth or fiction of that assumption.

If we assume 1.75A quiescent: Then positive and negative peaks would be 3.5A?
This implies at least 28V rails into an 8 ohm resistive load. And we probably want
to tack on another 7V or so to keep the drains of our MOSFETs from becoming
big capacitors (at 0V they are same cap as source). I think 35V rails make sense...
And power supplies than can deliver 3.5A on 50% duty cycle = 2A with a big cap...

The biggest challenge to safe operating area will be at 1/2 full rail voltage = 17.5V.
there we will also see 2.19A. And these multiply to 38.3W instantaneous peak power
in each output device. 50% duty cycle means the an average no higher than 19.2W
that each device needs to heatsink away....

Our 3.5A current limit means that 4 ohms loads won't get any louder...
Our 28V rails (plus 7V for drain bias) means that 16 ohms won't get any louder...
So, you ideally do want about 6 to 12 ohm load with this configuration.

Last edited by kenpeter; 21st December 2011 at 11:46 PM.
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Old 22nd December 2011, 12:04 AM   #29
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The source impedance of the N mosfet is 1 / 6.9S = 0.145R

Because it gets a boost from the BJT, the source impedance
of the P mosfet is probably close to zero. But effectively the
same 0.145R as our N, because it is a copy of the N source.
And not a direct zero ohm copy of the plate. This means our
load is still centered properly in the middle.

New output impedance with source impedance included is 0.17R,
and the new damping factor 46.4

------------

With any SRPP you want the load centered in the middle of the
current sensing resistor. And our output stage is also an SRPP
(unity gain and upside down), but SRPP none the less...

The triode SRPP is loaded at the top end of its sense resistor,
and this is not a mistake. Cathode impedance is not negligible.
Midpoint with cathode resistance figured in, is probably close
to the cathode (if not somewhere inside the triode where you
can't get at it anyways)...

Last edited by kenpeter; 22nd December 2011 at 12:16 AM.
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Old 22nd December 2011, 12:54 AM   #30
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Whoops! My earlier dissipation figures were based upon class AB math.
This output stage is class A, and max dissipation would be at quiescent.
1.75A * 35V = 61.25W per output device! And no breaks for 50% duty.

(You could trick it to be square law Class AB amp. Replace output sense
resistors with Schottky diodes, and shunt maybe 33R across Q1's VBE to
assure 20mA minimum flows at all times. Silicon Schottky diodes rated
for about 5A would probably give the right curves to cross like a 6L6.
I'm not saying this would sound any better, just idle a lot less hot...)

Last edited by kenpeter; 22nd December 2011 at 01:15 AM.
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