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Old 15th December 2011, 08:17 PM   #11
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What make is that 6H8C? Looks like Chinese?


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Old 16th December 2011, 12:48 AM   #12
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Default the schematic

OH....my brain must be damaged by the high voltage of the tube...

That schematic was a dual axial stepping motor controller.

the right schematic is here
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Old 16th December 2011, 01:38 AM   #13
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For DC purposes, you have a CCS at both top and bottom.
Won't one or the other win this fight and drag your signal
all the way toward the winning rail?

I see you trying to make the upper mosfet same impedance
as the lower, perhaps like the output stage of Aikido. But I
think the relationship too high impedance to remain stable...

You might look to give your upper gate a fixed DC offset?
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Old 16th December 2011, 02:16 AM   #14
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Hi Kenpeter

I think fixed DC offset will have thermal problem since the current of mosfet increase with the temperature significantly. What will happen when the upper mosfet current increase from 1.5A to 2.5A while the lower side is always 1.5A?

I don't think my design is so good because the distortion is still quite big. Can a global feedback lower down the distortion?

Another problem is that the DC offset is drift with the temperature. When power on there's about -800mV at the output. It drops to several mV after about 5 minutes. What do you think is the reason of the drifting?
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Old 16th December 2011, 03:39 PM   #15
DF96 is offline DF96  England
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Quote:
Originally Posted by siliconray
The MOSFET has 1300pf Cg so it needs low output impedance to drive, especially when the freq is high. SRPP because the output impedance is low.
As the MOSFET appears to be acting as a follower the gate input capacitance will be bootstrapped, so effectively made much smaller. SRPP can have low output impedance, but it has poor drive capability so it is just as well your capacitance is bootstrapped. Your SRPP is unbalanced (different cathode resistor values) so may have higher distortion than a classic balanced SRPP.
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Old 16th December 2011, 10:06 PM   #16
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Quote:
Originally Posted by siliconray View Post
Hi Kenpeter

I think fixed DC offset will have thermal problem since the current of mosfet increase with the temperature significantly. What will happen when the upper mosfet current increase from 1.5A to 2.5A while the lower side is always 1.5A?

I don't think my design is so good because the distortion is still quite big. Can a global feedback lower down the distortion?

Another problem is that the DC offset is drift with the temperature. When power on there's about -800mV at the output. It drops to several mV after about 5 minutes. What do you think is the reason of the drifting?
Distortion might be caused by Q3, fighting to see constant source current.
Your Tube SRPP is driving much lower than 33K, because the collector end
of that gate resistor is swinging in opposition to any drive current of SRPP.

The top MOSFET should not be trapped in a local loop that makes a CCS.
As you have it now, will also fight the lower CCS, and drift all over the place.
Just bias the gate with a resistive divider. And cap couple your SRPP to it.

If you were trying to make an active current source, something that works
like Nelson's Aleph? The lower MOSFET would be the better place to do it.
Can show you another circuit that would hopefully infringe less upon Nelson.

Last edited by kenpeter; 16th December 2011 at 10:15 PM.
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Old 16th December 2011, 11:52 PM   #17
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thanks kenpeter. I understand that Q3 is fighting to keep the ccs. As you predict most distortion is not caused by tube, but the solid. A res devider can reduce the distortion, but how to deal with the dc zero point drift? may be capacitor output have to be used?
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Old 17th December 2011, 12:08 AM   #18
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You miss the point. Cannot settle DC using a pair of equal impedance CCS.
No more than you can guess which direction debris will fly in a trainwreck???

Let one MOSFET determine the voltage. Let the other determine the current.
You may need to trim once, but will not need a capacitor on the output.

Last edited by kenpeter; 17th December 2011 at 12:28 AM.
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Old 17th December 2011, 12:27 AM   #19
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Something like this....

Top MOSFET and voltage divider set voltage.
Bottom MOSFET and current sensors set the
current, and current balance.

The sum of currents sensed by R5 + R6 will
mate for equal and opposite class A currents.
With a fixed total that does not fight itself.
MOSFETs don't need to match, only R5 R6 do...

SRPP is not battling against collector Q1,
Collector is working in your favor this time...
BJT wont be driven to saturation nor cutoff.
Won't hear Q1 struggle to recover anymore.

Ferrite bead prevents possible oscillation.

M1 does not need a bootstrap. C1 provides
the ability for drive to briefly exceed the rail.
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Last edited by kenpeter; 17th December 2011 at 12:49 AM.
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Old 17th December 2011, 12:49 AM   #20
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Threads merged and cleaned up. Siliconray please do NOT start multiple threads on the same topic in different forums. I suggest you carefully read the forum rules. In the event that there is any question that your posts might be interpreted as commercial speech please post in your own forum - that's what it is for.
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