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Old 9th February 2009, 07:27 PM   #1
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Default Splitting up power supply inductance

Is there any disadvantage to splitting up total power supply inductance across multiple chokes (besides the $ required to purchase multiple chokes) to attenuate ripple?

In PSUD, if I model a CLC with a 4.7u-4H-180u and compare it to a CLCLC with a 4.7u-2H-180u-2H-180u (splitting one 4H into two 2H and adding a C) I get much better ripple performance with the same voltage values.

It appears that splitting the total inductance into smaller LC segments has the same (or greater) benefit as splitting up the resistance into smaller RC segments to get orders of magnitude better attenuation of ripple.

Are there any stability issues, etc with doing this compared to splitting up total resistance into multiple RC segments?
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Old 9th February 2009, 08:08 PM   #2
rdf is offline rdf  Canada
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The best way to visualize it - ignoring for now interaction between sections - is each LC stage as an independent second order low pass filter. Inputs above the LC resonant frequency are ideally attenuated at 12 dB per octave. While a single LC with large choke starts attenuating at a lower frequency, two LC sections in series attenuate at 12+12 dB per octave, or twice as fast. Performance specifically at 60 and 120 Hz ripple frequencies of either topology depends on component values but, again assuming ideals, dual LC sections eventually always win.

A downside is series LC sections do interact, which makes them more prone to ringing. PSUD's current-step function is the best simple way to design around it. RC sections can't ring but also have poor regulation at DC.
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Old 9th February 2009, 08:59 PM   #3
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Thanks for the explanation rdf.

Is there an optimization that can be realized for each LC section similar to the RC section stuff discussed in Morgan Jones (first calculated be Scroggie, IIRC)?

I have a (somewhat) related question about rectifier forward current. I am using constant current loads in PSUD instead of resistive loads and I keep getting the "rectifier forward current exceeded at XX milliseconds" message in PSUD.

If I look at the I(D1) graph (current through the rectifier), it is exceeded at startup, but appears to level off below the max for the rectifier (.75 A for a 5AR4) at steady state. Is this a problem, ie is there much safety margin here? As an example, the message may say forward current is .77A at .165ms. Am I risking arc-over if at start-up if I see this message? I cannot correlate the current and time values in the error message to the I(D1) curve.

In other words, I am struggling to interpret this warning message in PSUD.

I mentioned that I am using constant current loads in PSUD because I found a post here in which Ray Moth suggests changing them to an equivalent resistive load because in actual use, things don't conduct the full current at startup, and the error message should (hopefully) disappear. My PS model has most of the load via a current tap before the final RC section with a small amount of current taken off of the last section for the driver tubes, and I cannot change the intermediate current tap to a resistive load.
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Old 9th February 2009, 10:00 PM   #4
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I think that I just figured out my error message problem by playing around with PSUD. The forward current in the error message is indeed the average steady state forward current, so it's probably a good idea to get under the max current limit for the rectifier.
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