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1st February 2003, 02:43 AM  #21  
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The driver current needed has NOTHING whatsoever to do with the dissipation of the following stage. 

1st February 2003, 07:39 AM  #22  
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I say different; do you believe me or notit's only your bussiness.
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1st February 2003, 04:46 PM  #23 
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A bit delayed reply
Joel
You asked me to shed some light to the "controversy"that you have regarding the problem with slew rate limit on your design. I have not done any SR calculations again, so i had to do my homework first. What i have found though, is, that in theory, both parties may be right. I will explain myself later on, but i think that you may check the validity of your calculations by a scope connected at the anode of the 71A and driving the 6f6 with a sinusoidal variable freq. generator. You may set the freq. low, say 500Hz, increase the volume up to the point that the output starts to clip, slightly back it up, and then start increasing the freq. and observe the freq. at which you will see clipping at the output.This will be quite a valid method, if your design does not have a global NFB network. Now to the path and some of the results of my homework which i would like to share with you. I always like to know where formulas derive from. Unfortunately i could not track the origin of the Slew Rate formulas in any book. So starting from the very essentials, i tried toback every step up with a previous equation. All that follows, is a compilation of formulas i found in many different books. There is the possibility that some (or all) of the logical matchings i did, be missleading. I tried to present them here in a trasparent way, so someone to be able to spot the mistake(s). Therefore,any comments are more than welcome. Basic equations: (Please, be patient. After all, it is only twelve!) (1) C=Q/V (2) Q=A*t (3) t=C*V/A (4) i=Ie^(t/T) (5) v=V[1e^(t/T)] (6) T=R*C (7) S=Imax/C (8) Ci=Cgk+[1+((mu*Rl)/(rp+Rl))]*Cgp (9) e(t)=Vp*sin2pi*f*t (10) de/dt=2pi*f*Vp*cos2pi*f*t (11) S=Vp*2pi*f (12) f=S/2pi*Vp Two electrodes spaced apart, potentialy form a capacitor C. Eq. (1) C=Q/V says that capacitance C (Farrads) is proportional to charge Q (Coulomb) of the two electrodes, and inv. prop. to potential difference V(Volts) btn the two electrodes. Eq. (2) Q=A*t "visualises" charge Q as the product of current flow A (Amperes) times time t (seconds). If we apply eq (2) into eq. (1), we get eq. (3) t=C*V/A which shows the time that the capacitor needs to be charged. In plane words: The higher the capacitance, the longer the charging time. The higher the voltage the cap has to be "charged"up to, the longer the charging time. The higher the current the charging source can supply, the shorter the charging time. The value of the charging current i in respect to time t is given by the exponential (e=2.718) equation (4) i=Ie^(t/T). "I" shows the initial current which is the max current the source can supply. The value of the capacitor voltage v in respect to time t is given by the eq. (5) v=V[1e^(t/T)]. "V" shows the final max voltage the cap will reach at an infinitive long time. In both eq. (4) and (5), symbol "T" is what we know as the "Time Constant" of a circuit, the product of the resistance times the capacitance of the circuit, shown by eq.(6) T=R*C Eq.(7) S=Imax/C is the familiar eq. of the Slew Rate S. This eq. did not fall from the skies.It's origin is eq.(5) v=V[1e^(t/T)]. We simply practice the sort of magic Harry Potter has taught us. This is it: We replace V by it's equivalent V=I*R and T by R*C. We get: v=I*R[1e^(t/RC)] Then, we differantiate the whole thing in respect to time. We get: dv/dt=(I/C)*e^(t/R*C). Why did we perform the differentiation? Because we had in mind to form an equation that expresses the Rate of Change of the voltage. The dv/dt is exactly this. But this is not enough. We want an equation that expresses the Maximum Rate of Change of the Voltage. We name this S(Slew Rate)and we have: S=[dv/dt]max=[(I/C)*e^(t/RC)]max We turn to some "limits" calculus and the previous eq. becomes: S=Imax/C, which is indeed eq (7). For this eq. to be of any practical use, we have to put some meaningful figures into it. To do this , we have to model the circuit into which this formula will be applied. The output resistance R of the driver, the max current Imax it can source, and the capacitance C it will charge. Eq. (8) Ci=Cgk+[1+((mu*Rl)/(rp+Rl))]*Cgp describes the input capacitance Ci of the triode. From this we see that Cgk is treated as it is. But Cgp is multiplied by what is enclosed in the brackets. This is the "Miller capacitance, which can be many times that of the Cgk, depending on the rp, the Rl, but mostly the mu of the tube. So pluging in the eq. (8) the data that Joel gave us for his 6F671A amp. namely Cgk=3.7pF, Cgp=4.7pF,mu=3 (and i figure rp=1750, Rl=4800) we get Ci=18.73pf. Unfortunately, 6F6 has to charge not only Ci, but it's own Co, which is 13pF plus some strays dye to wiring of minimum 20pf. Adding all these, makes for a C=52pF Putting this into eq.(7) S=Imax/C together with Joel's Imax=0.9mA, we get S=17.4V/uS How can we see where Joel's 71A will slew limit (suppose we are dealing with sinusoidal signal)? Eq.(9) e(t)=Vp*sin2pi*f*t describes such a sinusoidal signal. (Vp=peak voltage, pi=3.14) Harry Potter again, and the rate of change of this signal is de/dt=2pi*f*Vp*cos2pi*f*t eq. (10),so the maximum slew rate for a sinusoidal signal, is: S=Vp*2pi*f which is eq. (11). Solving for f, we get eq. (12): f=S/2pi*Vp, which shows the freq. f above which the stage will slew limit. Joel said that the output swing of the 71A is 80 volts. If this is meant to be Vpeak, then together with S=17.4, eq. (12) gives us f=34.6Khz. I wish that this is correct. I have my doupts though, and this is why: Eq. (7) S=Imax/C, is based on eq. (5) v=V[1e^(t/T)] (the value of the voltage v in respect to time t while the capacitor is charging). If in this equation we set t=T, we see that at the time t equal to R*C the capacitor will have reached 63.2% of the value that could reach, provided a very long charging time was available. (PS*) Some books commend that, appropriate charging is accomplished at t between 4T and 8T. I made a small table showing the relation of t=xT, the cap voltage and the respective Sx t=1T v=63.2%V e^1 S=S1 t=2T v=86.46%V e^2 S=S1/2.7 t=3T v=95.02%V e^3 S=S1/7.4 t=4T v=98.17%V e^4 S=S1/20 t=5T v=99.33%V e^5 S=S1/55 t=6T v=99.75%V e^6 S=S1/147 t=7T v=99.91%V e^7 S=S1/409 t=8T v=99.97%V e^8 S=S1/1226 We see that at t=3T (v=95%V) S is 1/7 of what we have assumed. I don't know which "t" knowledgable engineers are utilising on SR calculations. So Joel, i don't know who is correct and who is not. Eq. 17 found in many standard electronics text books Eq. 8 found in "Vacuumtube & Semiconductor Electronics", Jacob Millman (1958) McGrawHill Eq. 912 and the differentiation of eq.5, found in "Electronics"band of REA's "Problem Solvers" series, 1990, ISBN 0878915435 Regards George (PS*) There is one case in which, capacitor is fully charged in t=T. This happens when capacitor is charged with constant current i=I, that is, the value of the initial charging current. 
1st February 2003, 06:35 PM  #24 
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Yow!
I love algebra Tim 
1st February 2003, 10:28 PM  #25  
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Re: A bit delayed reply
Quote:
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1st February 2003, 10:33 PM  #26  
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SMART PEOPLE.
Hi,
Quote:
Cheers, \in HH style.
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2nd February 2003, 06:36 AM  #27 
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Originally posted byEC8010:
"At the instant that you substituted v=Vsin(2pi*f*t) you were constrained to a single frequency, and transient considerations became irrelevant".  EC8010 thank you for the positive confirmation of some of the equations i printed. As far as the "constraining" to a single frequency, i think that this is unavoidable, if someone chooses an analytical approach. Except if you are implying that i constrained myself to sinusoidal signals and didn't pay any attention to other signal forms. If this is the case, i am sure that once a reliable and (conservative) way of calculating the SR limit for sinusoidal signals is agreed to be accepted, there will be a way to deal with non sinusoidal waveforms as well. My main concern is still unanswered though: What "t" is prudent to be utilised in SR calculations, t=1RC, t=2RC, t=3RC......? My opinion is that t=1RC is not enough. I opt for t=3RC. The price to pay is that S becomes 1/7.4 of the one that is currently accepted (?) as adequate. I would like your comments please Regards George 
2nd February 2003, 09:55 AM  #28 
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George,
what I meant was that by invoking sine waves, your answer correctly predicted the highest (sinusoidal) frequency that could be handled. In these days of sharply bandwidthlimited (digital) signals, we can be very precise, and say that if it copes with a 20kHz sinewave (CD) then that is perfectly adequate because there are no transients containing frequencies higher than that. If we use LP or SACD etc, then we might wish to allow for a higher frequency. Considering voltage slew rates is an awkward way of looking at the problem, and is equivalent to replacing spark plugs via the big end. The problem is one of current. All we need to do is to calculate the reactance of our capacitor at the highest frequency of interest. We then find the highest voltage that could be applied without overloading the stage, and combine the two with Ohm's law to find the maximum current required. Because of the phase shift caused by a capacitor, this current is required when the applied voltage is zero. We then reach for the anode characteristics of the previous stage and their loadline, and plot the current swing above and below the operating point. If we combine those two points with the maximum voltage swing points, we have an elliptical loadline. We can now make an informed choice as to whether we need more quiescent current because we can look at the linearity of the stage as it delivers this current. I usually find that I want a lot more quiescent current in order to swing the (small) signal current with any degree of linearity. The results using this approach tend to agree with the various "rules of thumb" that have been suggested  with the difference that our choice is far more informed. I hope this clarifies matters.
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4th February 2003, 01:29 PM  #29 
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George,
Many thanks for your post. I have found that my amplifiers sound best with 5 times the calculated current drive available in the driver stage. If we assume in Class A that only half of the bias current level is available for drive in a driver stage  then I think this is inline with your three times RC suggestion... For those who disagree then I recommend you try it and see...if it works for you great  if it doesn't then you have not lost anything by trying it... It is perfectly possible in any given system, listened too by an individual for the low current driver to be preferred... ciao James 
4th February 2003, 05:22 PM  #30  
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Location: Brooklyn, NY

Quote:
If you choose to use a driver with 5 times that value, be my guest  but any difference, or "improvement" in sound is due to the lower mu, and differing plate resistances the high current tubes enjoy, as opposed to low current + high Rp + high mu tubes. I can't think of any situation where you could do a 1 to 1 switch and have a fair comparison. So, maybe we can't generalize like that. But don't get me wrong  I like the idea of a triode strapped 6V6, or 6BQ5 as a driver stage  but just because it's different  we've proven mathmatically that one doesn't need the current. 

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