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Old 14th March 2007, 12:18 AM   #1
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Default How to set the bias of a FET output stage?

Following the Bob Cordell thread on FET vs BJT (I'm still 40 pages back from the current post) I read all about biasing a FET output stage so that is doesn't change much with temperature. But I have looked at the different FET datasheets and cannot figure out how to determine what level of bias current will achieve this. In testing I seem to have stumbled on the right bias for a 2SK1058/2SJ162 pair with my set up at about 105mA. I want to also test the 2SK1530/2SJ201 pair at the right bias but again I don't know how to determine except to take a shot in the dark and then test, change, etc. Is there a way to determine from the datasheets for the FETs?

In Bob Cordell's FET amplifier doc. he has a graph on page 6, Figure 4 where he does this testing by running with 1/8 power until warm and then turning off the input signal and seeing where the bias current goes too over time. This is basically what I did on the 2SK1058/2SJ162's but pretty much just got lucky because I started right around 100mA. My main question is how to determine without this long drawn out testing and re-testing? Or at least, how to pick a good starting point so testing is limited and how to determine the starting point?

Other questions: Is determining the bias of a FET output stage this way a good way to set it or should some thermal tracking be involved using something like a Vbe multiplier considered a better approach? Power dissipation can get pretty high and I know FET output stages are biased hotter but how hot is too hot? I am using +/-50V supplies so 100mA is 10W of power dissipation which is not bad but at 200mA that is quite a bit of power dissiptaion for a ~125W/ch (8 ohm) amp. Still learning lots so maybe not a lot but seems like a lot to me. I am using a simple source follower output stage, one device per side.

Thanks,
-SL
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Old 14th March 2007, 12:36 AM   #2
GK is offline GK  Australia
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Those are lateral MOSFET's, so finding the stable bias point is easy.

Refering to this datasheet.....


http://www1.jaycar.com.au/images_uploaded/2SK10568.PDF


.....all you need to do is look at the Drain Current Vs Gate-Source voltage transfer charachteristic graph (on the bottom right hand side of page 4).
The stable bias point is where the three temperature plots intersect each other, which, for the devices you have chosen, is at a tad above100mA.

Cheers,
Glen
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Old 14th March 2007, 04:47 PM   #3
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Glen,

Thank you for the response. I see now on the graph that it is easy to determine on the 1058 part. The 2SJ162 PFET has an intersection less than the 1058 NFET around 80mA. I figure the higher bias is the correct setting. If I can ask about another pair of devices, the 2SK1530/2SJ201 pair. The intersection is right about 8A for the NFET 1530 while the 2SJ201 doesn't seem to intersect on the graph so above 12A. How would a pair of these devices be biased? Surely not at 8A but somewhere in the hundreds of mA. Or is it that the approach would be to have thermal tracking for these devices since to get thermal bias stability without tracking it just not possible like the 1058/162 pair? Sorry if these are rather dumb questions, still trying to learn after years of working with chip amps only.

Thanks again.
-SL
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Old 14th March 2007, 10:49 PM   #4
AndrewT is offline AndrewT  Scotland
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Hi,
the consensus seems to be that the optimum bias setting found in BJT output stages does not exist for FET output stages.
It appears that more is better.

Borbely is more extreme than most and recommends a minimum of 500mA for a stage and >100mA for each FET pair.
This will make any amp run HOT
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Old 15th March 2007, 01:54 AM   #5
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I use 100mA for each lateral MOSFET pair -- works very OK for me.
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Old 15th March 2007, 02:23 AM   #6
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Default Re: How to set the bias of a FET output stage?

Quote:
Originally posted by SpittinLLama
Following the Bob Cordell thread on FET vs BJT (I'm still 40 pages back from the current post) I read all about biasing a FET output stage so that is doesn't change much with temperature. But I have looked at the different FET datasheets and cannot figure out how to determine what level of bias current will achieve this. In testing I seem to have stumbled on the right bias for a 2SK1058/2SJ162 pair with my set up at about 105mA. I want to also test the 2SK1530/2SJ201 pair at the right bias but again I don't know how to determine except to take a shot in the dark and then test, change, etc. Is there a way to determine from the datasheets for the FETs?

In Bob Cordell's FET amplifier doc. he has a graph on page 6, Figure 4 where he does this testing by running with 1/8 power until warm and then turning off the input signal and seeing where the bias current goes too over time. This is basically what I did on the 2SK1058/2SJ162's but pretty much just got lucky because I started right around 100mA. My main question is how to determine without this long drawn out testing and re-testing? Or at least, how to pick a good starting point so testing is limited and how to determine the starting point?

Other questions: Is determining the bias of a FET output stage this way a good way to set it or should some thermal tracking be involved using something like a Vbe multiplier considered a better approach? Power dissipation can get pretty high and I know FET output stages are biased hotter but how hot is too hot? I am using +/-50V supplies so 100mA is 10W of power dissipation which is not bad but at 200mA that is quite a bit of power dissiptaion for a ~125W/ch (8 ohm) amp. Still learning lots so maybe not a lot but seems like a lot to me. I am using a simple source follower output stage, one device per side.

Thanks,
-SL

Glen is right. Unfortunately, the zero-temperature-coefficient for MOSFETs like HEXFETs lies at an operating current that is usually impractically high. For such FETs, you'll end up biasing them below this current level and will need to use some temperature-compensated bias scheme, such as the Vbe multiplier used for bipolar output stages.

Bob
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Old 15th March 2007, 08:41 AM   #7
GK is offline GK  Australia
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Quote:
Originally posted by SpittinLLama
Glen,

Thank you for the response. I see now on the graph that it is easy to determine on the 1058 part. The 2SJ162 PFET has an intersection less than the 1058 NFET around 80mA. I figure the higher bias is the correct setting. If I can ask about another pair of devices, the 2SK1530/2SJ201 pair. The intersection is right about 8A for the NFET 1530 while the 2SJ201 doesn't seem to intersect on the graph so above 12A. How would a pair of these devices be biased? Surely not at 8A but somewhere in the hundreds of mA. Or is it that the approach would be to have thermal tracking for these devices since to get thermal bias stability without tracking it just not possible like the 1058/162 pair? Sorry if these are rather dumb questions, still trying to learn after years of working with chip amps only.

Thanks again.
-SL

I've never tried an output stage with the 2SK1530/2SJ201 pair, unfortunately. For optimal bias stability, those devices would need some degree of temperature compensation, but if you look at the graphs, those devices are not all that bad, temp. co. wise. The dastsheet I've got for the 2SK1530 gives Id/Vgs curves for -40degC, 25degC and 125degC. For that huge temperature range, there is about a 200mA Id variation for a given Vgs at bias currents below 500mA.
Once warmed up, an output stage should never experience such a huge variation in temperature, so the drift will be much lower. I guess you could just bias these devices heavily at 2 or 3 hundred mA and live with 50-100mA or so of bias current current variation.
Also, I'm not really into MOSFET's, but I'm pretty sure that the 2SK1530/2SJ201 are obsolete and pretty scarce. Most people these days use HEXFET's, but these devices must be temperature compensated, typically with a Vbe multiplier as Bob has already mentioned. If you look up the temp. co. graphs of a popular HEXFET for audio such as the N-channel IRFP240 and compare it to the 2SK1530, you'll immediately see why.

Cheers,
Glen
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Old 15th March 2007, 10:14 AM   #8
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Default Re: How to set the bias of a FET output stage?

Quote:
Originally posted by SpittinLLama

...
In Bob Cordell's FET amplifier doc. he has a graph on page 6, Figure 4 where he does this testing by running with 1/8 power until warm and then turning off the input signal and seeing where the bias current goes too over time. This is basically what I did on the 2SK1058/2SJ162's but pretty much just got lucky because I started right around 100mA. My main question is how to determine without this long drawn out testing and re-testing? Or at least, how to pick a good starting point so testing is limited and how to determine the starting point?
...
Thanks,
-SL

Hi SpittenLLama,
As other members have stated, there isnít a clear optimum bias current. Concerning the 2SC1530/2SJ201 pair, I have spiced these devices, based on the data sheets as well as measurements on some real devices. It shows up, by simulation, that a bias of 125mA is quite adequate. Below 100mA distortion rises markedly. Beyond 150mA not much is gained. A couple of year ago I wrote an article about an autobias circuit for vertical MOSFETs, published in EW, December 2003. Maybe, this might be of interest to you. Please let me know and Iíll send a pdf copy to you.
Cheers,
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Old 15th March 2007, 03:57 PM   #9
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Thanks so much for the post to everyone. I had the 1530/201 at 100 - 125mA but after running power into a resistive 8 ohm load the bias current is up at 300mA, give or take. My heat sinks are a little under sized so more stability would be obtained using better heat sinks. I also noticed that the harmonics (FFT) drop down like JackinNJ said and there really isn't much decrease in harmonics with higher bias. There is some decrease but at the expense of so much more power dissipation I don't think the trade-off is worth it. Always about trade-offs.

Again, thanks to all. I feel like I now understand that for FETs like the 1058/162, they can be easily biased with out temperature compensation while those that have a zero crossing at a much higher current will need some sort of temp. comp. I was using a Vbe multiplier with a BD139 but was also trying a much simple bias scheme and trying to figure it all out. I guess I could also do as Glenn suggested and bias at a point and see where it goes from there when running. Might be fine either way.

Now to figure out what BJT is best for which FETs. I have a bunch of BD139 and BD140 parts. FYI, I am using a LM4702 so bias can be as simple as a resistor. Still trying to get THD+N below 0.001% but can't seem to get there, only at < 0.003%.

I will look at the HEXFETs. Any other suggestions for output stage fETs. I need to check out the IRFP240 and it's complement.

Estuart, I'd love to read the article. You can send it to dianeone at comca$t dot n3t. Trying to avoid spam (no idea if being more clear will cause spam) so let me know if that is not clear.

I learn so much from this place. Great site.
-SL
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Old 16th March 2007, 07:36 AM   #10
AndrewT is offline AndrewT  Scotland
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Hi,
irfp240 is usually complemented with irfp9240. These work @ upto +-95Vdc.
A better pairing is irfp240/9140 but you are limited to <+-50Vdc.

These vFETs are not cheap, you will find that the quasi complementary output stage using just Nchannel FETs can be built cheaper. irfp540 and 640 are very cheap and you can afford to fit more pairs and spread them along a thinner (=cheaper) heatsink. The usual bias rule applies to the quasi comp.

Look at the quasi threads (there are now 4 variations).
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