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Old 11th November 2006, 12:21 PM   #1
ash_dac is offline ash_dac  United Kingdom
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Default Bootstrapped FET source follower ?

Hi,

Sevin, Leonce J., "Field-Effect Transistors," Texas Instruments Incorporated, McGraw-Hill, 1965, pp. 65-67.

Has anyone used / built a bootstrapped FET source follower ? Or is it just a fancy name for a standard circuit?

Info' here but I do have the book:-

"For driving a low impedance load, the best approach that I've
found to date is to use what is know as a bootstrapped source follower. Here, a PNP bipolar is added to the circuit. The drain is connected to the supply by a resistor, possibly with a choke in series. The base of the PNP device is connected to the drain, and the emitter to supply with an appropriate biasing resistor, as well as AC bypassed to the supply. The PNP collector is connected to the FET source. If the drain to supply impedance is sufficiently high, this has the effect of multiplying the gm of the FET by the hfe of the PNP bipolar."

http://groups.google.co.uk/group/rec...be350f0822cc62
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Old 11th November 2006, 12:48 PM   #2
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sounds like CFP/Sziklai connection to me.
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Old 11th November 2006, 02:55 PM   #3
ash_dac is offline ash_dac  United Kingdom
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Quote:
Originally posted by darkfenriz
sounds like CFP/Sziklai connection to me.

Click the image to open in full size.

Some capacitancs are incorrect.
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Old 11th November 2006, 03:39 PM   #4
ilimzn is offline ilimzn  Croatia
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Quote:
Originally posted by ash_dac
Some capacitancs are incorrect.
Alomg with other things in the schematic!

It is indeed a CFP connection, and it's simple - two transistors and 3 or 4 resistors. Simplest version:

1) gate of FET connects input and to ground via resistor, this will be the input impedance resistive part.
2) source of N ch FET connects to collector of PNP BJT, output cap, and via resistor to ground, this will approximately equal the output impedance.
3) drain of fet connects to base of BJT and to + rail via resistor
4) emitter of BJT connects to + rail. Alternatively, emitter connects to +rail via small resistor that is in parallel with an AC bypass cap.
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Old 11th November 2006, 04:17 PM   #5
ash_dac is offline ash_dac  United Kingdom
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Quote:
Originally posted by ilimzn


Alomg with other things in the schematic!

It is indeed a CFP connection, and it's simple - two transistors and 3 or 4 resistors. Simplest version:

1) gate of FET connects input and to ground via resistor, this will be the input impedance resistive part.
2) source of N ch FET connects to collector of PNP BJT, output cap, and via resistor to ground, this will approximately equal the output impedance.
3) drain of fet connects to base of BJT and to + rail via resistor
4) emitter of BJT connects to + rail. Alternatively, emitter connects to +rail via small resistor that is in parallel with an AC bypass cap.
Thanks.

See attached (sorry for the poor quality picture). Will stability be a problem ?
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File Type: jpg f1.jpg (20.0 KB, 464 views)
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Old 11th November 2006, 04:56 PM   #6
forr is offline forr  France
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Hi Ash_Dac,
Q1 should be a PNP on your schematics. It is not the FET which is bootstrapped but the input biasing resistor. As considering a CFP FET follower, you may be interested to be aware that Linsley-Hood published a very simple push-pull buffer using two of them with complementary polarity.
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Old 11th November 2006, 10:16 PM   #7
ilimzn is offline ilimzn  Croatia
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On the schematic in ash_dac's first post, the power rail is negative (note -6V).

@ash_dac, this is not a good way to draw schematics, with a + end of a voltage source made negative by making the voltage source negative - it works in the sim of course, but confuses anyone who is reading the schematic needlessly.

In your second post, the lefthand schematic is the double bootstrap follower, this keeps the FET at constant Vds. There are also easyer ways of doing this with a single BJT and capacitor bootstrap. Bootstrapping in this manner may be problematic for stability, thoug, and is only used when the utmost lowest input capacitance to the follower is needed.
The righthand schematic is what I was talking about, although it is customary to put a resistor between B and E of the BJT. In low frequency operation it is not strictly required, but at HF you get charge storage effects in the B-E junction of the BJT, the resistor is essentially a part to discharge it. In this schematic Cgs is made mostly invisible by bootstrapping the source, but Cgd remains. For a small siglan fet similar to BF245, this will decrease the input capacitance but at most by half, since for such symetrical FET architectures, where D and S are interchangeable, Cgs and Cgd are roughly the same.
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Old 14th November 2006, 07:31 PM   #8
ash_dac is offline ash_dac  United Kingdom
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Thankyou for your replies.

I have looked at the IGBT (have seen a JLH IGBT design for Toshiba). I understand this to be like a darlington with mosfet input and bipolar output (with possiblity of latching up)

Is there an equivalent CFP IGBT ?
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Old 14th November 2006, 07:46 PM   #9
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IGBT is equivlent to CFP, not darlington.
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Old 14th November 2006, 08:01 PM   #10
ash_dac is offline ash_dac  United Kingdom
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Quote:
Originally posted by darkfenriz
IGBT is equivlent to CFP, not darlington.
Thanks...

Even more interested now.

What are the limitations of these devices ; the latch up problem, input capacitance ?
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