Re: Just don't get this ........
Read this
http://www.jefspalace.be/analog/input stage/constant current source.php
lineup said:
Read this
http://www.jefspalace.be/analog/input stage/constant current source.php
In Jef's current source current depends on Q3's Vbe (on first schematic). In Your CS current depends on supply voltage, because Q3-Q6 seems (at least for me 
) like a just slightly complicated current mirror.
Another thing: what is C7 purpose? I think it doesn't much in frequency compensation. Higher frequency voltage on Q11 collector is very small (due to C5). I saw this in many similar schematic and still don't understand, so if anyone can explain .... Maybe C5 is equal to input capacitance of output stage, then all becomes symmetrical and all right
) like a just slightly complicated current mirror.Another thing: what is C7 purpose? I think it doesn't much in frequency compensation. Higher frequency voltage on Q11 collector is very small (due to C5). I saw this in many similar schematic and still don't understand, so if anyone can explain
.... Maybe C5 is equal to input capacitance of output stage, then all becomes symmetrical and all right 
javascript:smilie('
viktor
this version is the best version so far, in my opinion
and this is the first version that could be called Hifi
A detail:
Because different exemplars of JFET can be very different,
you will have to adjust R7 (400 Ohm)
until you get the current you want to have
- in first input pair Q1,Q2
- which also will effect important current in Q10 - Q12, second stage
As I posted in another post,
I recommend Q10 and Q12 should have like 20-30 mA,
for driving 2 parallel pairs of mosfet of in good way.
This means you should have 40-60 mA through R21 (47 Ohm).
( My target value:
10-15mA per paralleled push-pull pair of output mosfet 2SK1058 / 2SJ162 )
If no other readers find some details that should be modified,
then you can start buying and building.
Regards
lineup
this version is the best version so far, in my opinion
and this is the first version that could be called Hifi
A detail:
Because different exemplars of JFET can be very different,
you will have to adjust R7 (400 Ohm)
until you get the current you want to have
- in first input pair Q1,Q2
- which also will effect important current in Q10 - Q12, second stage
As I posted in another post,
I recommend Q10 and Q12 should have like 20-30 mA,
for driving 2 parallel pairs of mosfet of in good way.
This means you should have 40-60 mA through R21 (47 Ohm).
( My target value:
10-15mA per paralleled push-pull pair of output mosfet 2SK1058 / 2SJ162 )
If no other readers find some details that should be modified,
then you can start buying and building.
Regards
lineup
!
I will match JFET-s with 2.5mA and 15-20V DC D-S
lineup said:viktor
this version is the best version so far, in my opinion
and this is the first version that could be called Hifi
A detail:
Because different exemplars of JFET can be very different,
you will have to adjust R7 (400 Ohm)
until you get the current you want to have
- in first input pair Q1,Q2
- which also will effect important current in Q10 - Q12, second stage
As I posted in another post,
I recommend Q10 and Q12 should have like 20-30 mA,
for driving 2 parallel pairs of mosfet of in good way.
This means you should have 40-60 mA through R21 (47 Ohm).
( My target value:
10-15mA per paralleled push-pull pair of output mosfet 2SK1058 / 2SJ162 )
If no other readers find some details that should be modified,
then you can start buying and building.
Regards
lineup
I will match JFET-s with 2.5mA and 15-20V DC D-S
Okay.
But you do not have to match them.
Not in this case.
Besides you will have to try VERY VERY many to find a close matched pair of JFET ....
Just pick two JFET exemplar, of that sort you want to use.
Those look like be 2N5484 and 2N5486.
But you can use many different JFET, for example 2SK170.
What type is not in any way critical as long as you make R6 big enough,
and so not leave more than 20-25 Volt across that 2N5484.
Or whatever max Vds JFET has.
(Frankly, I don't know what that upper 2N5486 is doing there: I would not need it!
Maybe someone will tell us what good (or bad ) this 2N5486 is doing ...)
Make a circuit with 40-50 VDC.
You can connect R6 (12 kOhm) temporary to 0 Volt, for this testing.
If you use your 2 x 50 VDC supply for this amplifier.
a) Then put them JFET into place. Together with R7 and R6.
b) Try with R7=390 Ohm
c) Measure current ( for exemple voltage across R6 /12000 )
d) If is too much current, increase resistance, try with R7=470 Ohm
....If is too little current, decrease resistance, try R7=330 Ohm
e) Measure and repeat until you get 2.5 mA,
or whatever current you want this CCS, current source, to give
lineup
But you do not have to match them.
Not in this case.
Besides you will have to try VERY VERY many to find a close matched pair of JFET ....
Just pick two JFET exemplar, of that sort you want to use.
Those look like be 2N5484 and 2N5486.
But you can use many different JFET, for example 2SK170.
What type is not in any way critical as long as you make R6 big enough,
and so not leave more than 20-25 Volt across that 2N5484.
Or whatever max Vds JFET has.
(Frankly, I don't know what that upper 2N5486 is doing there: I would not need it!
Maybe someone will tell us what good (or bad
) this 2N5486 is doing ...)Make a circuit with 40-50 VDC.
You can connect R6 (12 kOhm) temporary to 0 Volt, for this testing.
If you use your 2 x 50 VDC supply for this amplifier.
a) Then put them JFET into place. Together with R7 and R6.
b) Try with R7=390 Ohm
c) Measure current ( for exemple voltage across R6 /12000 )
d) If is too much current, increase resistance, try with R7=470 Ohm
....If is too little current, decrease resistance, try R7=330 Ohm
e) Measure and repeat until you get 2.5 mA,
or whatever current you want this CCS, current source, to give
lineup
OK, here's a slightly more detailed analysis...
1) R18, C5, C7
C7 would be Cdom only if C5 is removed completely and R18 adjusted for approximately equal voltage swing on collector of Q11 and Q12. Otherwise, C7 only sees milivolts of swing at HF so it's effectiveness is dubious. The problem is, you cannot adjust R18 to satisfy this.
Unlike the swing on C of Q12 (approximately = amplifier output), the swing on C of Q11 would be proportional to the actual current required to drive the output stage - essentially the error voltage between input and output of the output follower, that can have considerable distortion, especially with complex loads and MOSFETs: because they require current only to drive their nolinear Ciss, distorted to begin with, it gets worse with increased frequency because amplitude goes up. Potentially, it can get disastrous at clipping and especially at current limiting. This distorted waveform is additionally counterphase (although with differing amplitude) between Cs of Q11 and Q12, therefore nto common mode and it's effects are not cancelled by the LTP action. This all should be kept in mind because Vcb acts on a nonlinear Ccb in the BJT's of the driver stage, componding an already present distortion mechanism.
A way to largely reduce this problem can be seen in Quasi's design, as well as Symasym: what is Q11 in your design, is cascoded with another transistor with it's B on the output rail. This makes the voltage swing on Q11 and Q12 collectors approximately equal.
This has another desirable effect: A simulation will reveal that for most situations, the power dissipation of Q11 and Q12 will be nearly the same, so the offset introduced in the driver stage will be minimal. Similairly, the cascode transistor and what is Q10 in your design, will have similar power dissipation, but as long as Q9 and Q10 are thermally coupled, this will not influence offset. The low gm of the MOSFETs can. however, introduce an error, due to a part of the required sqing on C of Q12 that is proportional with output current (*), which can be signifficant due to low gm. A slight modification of the cascoding scheme is possible, which eqalizes the voltage swing on Q11 and Q12 collectors neraly perfectly, and also balances the current mirror, but I'm not going to reveal all my tricks
(*) There is a non-obvious danger of instability here, present also in single ended VAS designs. The voltage driving the output stage is a superposition of the required output voltage, and a voltage proportional to the output current, which will be out of phase for a reactive load - for low gm devices the latter can be quite high, especially for low load impedances. Being OUT OF PHASE, it makes the driver output also out of phase, and this is fed back through the miller comp ensation cap!
2) R19, R20
R19 and R20 are the same as input LTP, but this stage has an order of magnitude higher tail current. This is severe degeneration, more so given that the beta the BJTs in this stage is much lower than that of the input ones. You lose signifficant open loop gain. Still, degeneration is beneficial for linearity and stability, so keep it but use sensible values.
Here is a trick to make degeneration adjustable with a single resistor per stage, preserving symetrical clipping of the driver stage and DC conditions:
Make R21 into two resistors, 100 ohm each, one per emitter of Q11 and Q12. Then connect a resistor between the emitters, on the order of single digit ohms for this stage. No resistor, the amp is not differential. With a short, it is a non-degenerated LTP. Degeneration increases with the E-to-E resistor, n ohm or three will probably suffice. A similar thing for the input stage: split R6 into 2x 22 or 24k, once per E of input LTP BJTs, connect 18-22 ohms E-to-E. Varying this resistor changes degeneration without affecting DC conditions.
3) Driver/input stage power supply
Given a saturation voltage of 12V for the LMOS outputs, and drop on said resistors, let's investigate how we can optimize the driver and output power supply.
First, lets see if we can alow the input and driver stage to clip, without introducing unwanted charge storage effects. In this design, we can, because stage currents are strictly limited, by the input LTP tail CCS. In both stages current swing = tail current, there is nothing to oversaturate the BJTs. This is VERY important, it tells us what happens when the output stage clips for any reason. From this standpoint, this design is trouble-free, so we look at the output stage.
b)The overriding consideration here is LMOS Rdson and saturation. At Vgsmax (15V), this approaches 0.8 ohms - at Idmax, Vds will be 5.6V worst case. For this we need 15V Vgs, so it follows that the driver should be able to produce 9.4V more than the drain voltage, that being the output stage power rail. Driver rail should be a bit higher than output rail plus 9.4V, to account for the drop in the drived, about 2V here. How about clipping?
If the driver rail is equal to the output rail, then Vds will be higher than Idmax * Rdson. At Vd=Vg, 12V Vgs is required at 7A output current. The actual Vdg will be equal to driver voltage drop, so >0, However, this will only help a little - expect about 12-13V drop on the LMOS at maximum current - nearly 2.5 times that of the previous example. This means the dissipated power increases faster than load impedance decreases. Worse, current limiting the MOSFET may be no help - decreasing current increases voltage drop, but because saturation characteristic is nonlinear, curent limiting may even make things worse.
Regarding clipping, in the first case, the LMOS can always be driven to saturation, but for les than maximum current, ripple in the power rail will be routed to the output, during the clipped portion of the waveform. For the second case, this happens at maximum load and decreases with lower loads, the mechanism being feedthrough of the input stage clipping, since both see the same power supply ripple. It can be reduced by filtering - a moot point given the heat dissipation penalty.
A middle way is required. Obviousy a well filtered driver stage power supply (good short-term stiffness), preventing ripple feedthrough when driver is clipping, but this does not reduce the power dissipation penalty. We need a higher supply for the driver stage for that.
Can we get both, without another pair of power rails? There is, and it can be achieved in this design by rather curious means: the power supply rail has to be dimensioned to have about 11-12V ripple at maximum current.
Say what??? More ripple for better clipping? Here is how: The input stage, fed through a diode from the main rails, will catch the peak of the ripple in a local filter cap. At 12V ripple, it will be 11.4V OVER the lowest voltage of the power rail. 11.4V should cover the required 9.4V of Vg to Vd difference for good saturation, plus 2V lost in the driver stage. More than that and the bottom part of the power rail ripple gets through the saturated LMOS to the output in the clipped portions of the waveform. Any less, and the Vds and heat dissipation at clipping and Idmax rises. Less load means less ripple and less Vgs headroom, but also less load current, and with it, less required Vgs. With good filtering on the driver supply side provides minimum ripple feed through to the output when driver clips. It should also be noted that voltage drops in the driver or subsequent filtering of the driver rails should be taken into account and the power rail ripple RISED by that amount, if dissipation is to be minimized retaining gracefull clipping. Note that anything over 9.4V or so required for LMOS saturation increases the power dissipation penalty, and, also, do not take 9.4V as gospel - fine tweaking is necessary, as the 9.4V value is derived from worst case datasheet values.
So there, you learned a trick today
4) 0.1 ohm resistors in LMOS sources
Given the high Rdson, these will do nothing to balance load current sharing. They would at 0.5-1 ohms but this will further reduce the already low gm, and increase required drive voltage. Remove them, do some minimal work at LMOS pairing and properly estimate the protection fuse ratings. The low and flatter gm of the LMOS helps. Here is what to do:
Measure Vgs at known current Id (make it high, 1-2A) of your LFETs, at Vgd=0 (short G and D). Select pairs so that there is least difference Vgs a pair. Within a pair, there will be a higher Vgsh, and a lower, Vgsh.
Measure current through the LMOS with Vgsh, at Vgsl. It will be lower than the one used for the initial measurement, call it Idl. Chose the worst case Idl out of all pairs (both P and N).
Find maximum current at 50V (or your chosen output stage rail voltage) on the SOA graph, using the line of your choice (DC if you want to be dead sure, 100ms if you trust your fuses to blow quickly, or somewhere inbetween), call it Imax.
Calculate maximum fuse rating as Imax * (1 + Idl/Id).
You will find that using Imax * 1.5 is a safe bet with LMOS.
1) R18, C5, C7
C7 would be Cdom only if C5 is removed completely and R18 adjusted for approximately equal voltage swing on collector of Q11 and Q12. Otherwise, C7 only sees milivolts of swing at HF so it's effectiveness is dubious. The problem is, you cannot adjust R18 to satisfy this.
Unlike the swing on C of Q12 (approximately = amplifier output), the swing on C of Q11 would be proportional to the actual current required to drive the output stage - essentially the error voltage between input and output of the output follower, that can have considerable distortion, especially with complex loads and MOSFETs: because they require current only to drive their nolinear Ciss, distorted to begin with, it gets worse with increased frequency because amplitude goes up. Potentially, it can get disastrous at clipping and especially at current limiting. This distorted waveform is additionally counterphase (although with differing amplitude) between Cs of Q11 and Q12, therefore nto common mode and it's effects are not cancelled by the LTP action. This all should be kept in mind because Vcb acts on a nonlinear Ccb in the BJT's of the driver stage, componding an already present distortion mechanism.
A way to largely reduce this problem can be seen in Quasi's design, as well as Symasym: what is Q11 in your design, is cascoded with another transistor with it's B on the output rail. This makes the voltage swing on Q11 and Q12 collectors approximately equal.
This has another desirable effect: A simulation will reveal that for most situations, the power dissipation of Q11 and Q12 will be nearly the same, so the offset introduced in the driver stage will be minimal. Similairly, the cascode transistor and what is Q10 in your design, will have similar power dissipation, but as long as Q9 and Q10 are thermally coupled, this will not influence offset. The low gm of the MOSFETs can. however, introduce an error, due to a part of the required sqing on C of Q12 that is proportional with output current (*), which can be signifficant due to low gm. A slight modification of the cascoding scheme is possible, which eqalizes the voltage swing on Q11 and Q12 collectors neraly perfectly, and also balances the current mirror, but I'm not going to reveal all my tricks
(*) There is a non-obvious danger of instability here, present also in single ended VAS designs. The voltage driving the output stage is a superposition of the required output voltage, and a voltage proportional to the output current, which will be out of phase for a reactive load - for low gm devices the latter can be quite high, especially for low load impedances. Being OUT OF PHASE, it makes the driver output also out of phase, and this is fed back through the miller comp ensation cap!
2) R19, R20
R19 and R20 are the same as input LTP, but this stage has an order of magnitude higher tail current. This is severe degeneration, more so given that the beta the BJTs in this stage is much lower than that of the input ones. You lose signifficant open loop gain. Still, degeneration is beneficial for linearity and stability, so keep it but use sensible values.
Here is a trick to make degeneration adjustable with a single resistor per stage, preserving symetrical clipping of the driver stage and DC conditions:
Make R21 into two resistors, 100 ohm each, one per emitter of Q11 and Q12. Then connect a resistor between the emitters, on the order of single digit ohms for this stage. No resistor, the amp is not differential. With a short, it is a non-degenerated LTP. Degeneration increases with the E-to-E resistor, n ohm or three will probably suffice. A similar thing for the input stage: split R6 into 2x 22 or 24k, once per E of input LTP BJTs, connect 18-22 ohms E-to-E. Varying this resistor changes degeneration without affecting DC conditions.
3) Driver/input stage power supply
Given a saturation voltage of 12V for the LMOS outputs, and drop on said resistors, let's investigate how we can optimize the driver and output power supply.
First, lets see if we can alow the input and driver stage to clip, without introducing unwanted charge storage effects. In this design, we can, because stage currents are strictly limited, by the input LTP tail CCS. In both stages current swing = tail current, there is nothing to oversaturate the BJTs. This is VERY important, it tells us what happens when the output stage clips for any reason. From this standpoint, this design is trouble-free, so we look at the output stage.
b)The overriding consideration here is LMOS Rdson and saturation. At Vgsmax (15V), this approaches 0.8 ohms - at Idmax, Vds will be 5.6V worst case. For this we need 15V Vgs, so it follows that the driver should be able to produce 9.4V more than the drain voltage, that being the output stage power rail. Driver rail should be a bit higher than output rail plus 9.4V, to account for the drop in the drived, about 2V here. How about clipping?
If the driver rail is equal to the output rail, then Vds will be higher than Idmax * Rdson. At Vd=Vg, 12V Vgs is required at 7A output current. The actual Vdg will be equal to driver voltage drop, so >0, However, this will only help a little - expect about 12-13V drop on the LMOS at maximum current - nearly 2.5 times that of the previous example. This means the dissipated power increases faster than load impedance decreases. Worse, current limiting the MOSFET may be no help - decreasing current increases voltage drop, but because saturation characteristic is nonlinear, curent limiting may even make things worse.
Regarding clipping, in the first case, the LMOS can always be driven to saturation, but for les than maximum current, ripple in the power rail will be routed to the output, during the clipped portion of the waveform. For the second case, this happens at maximum load and decreases with lower loads, the mechanism being feedthrough of the input stage clipping, since both see the same power supply ripple. It can be reduced by filtering - a moot point given the heat dissipation penalty.
A middle way is required. Obviousy a well filtered driver stage power supply (good short-term stiffness), preventing ripple feedthrough when driver is clipping, but this does not reduce the power dissipation penalty. We need a higher supply for the driver stage for that.
Can we get both, without another pair of power rails? There is, and it can be achieved in this design by rather curious means: the power supply rail has to be dimensioned to have about 11-12V ripple at maximum current.
Say what??? More ripple for better clipping? Here is how: The input stage, fed through a diode from the main rails, will catch the peak of the ripple in a local filter cap. At 12V ripple, it will be 11.4V OVER the lowest voltage of the power rail. 11.4V should cover the required 9.4V of Vg to Vd difference for good saturation, plus 2V lost in the driver stage. More than that and the bottom part of the power rail ripple gets through the saturated LMOS to the output in the clipped portions of the waveform. Any less, and the Vds and heat dissipation at clipping and Idmax rises. Less load means less ripple and less Vgs headroom, but also less load current, and with it, less required Vgs. With good filtering on the driver supply side provides minimum ripple feed through to the output when driver clips. It should also be noted that voltage drops in the driver or subsequent filtering of the driver rails should be taken into account and the power rail ripple RISED by that amount, if dissipation is to be minimized retaining gracefull clipping. Note that anything over 9.4V or so required for LMOS saturation increases the power dissipation penalty, and, also, do not take 9.4V as gospel - fine tweaking is necessary, as the 9.4V value is derived from worst case datasheet values.
So there, you learned a trick today
4) 0.1 ohm resistors in LMOS sources
Given the high Rdson, these will do nothing to balance load current sharing. They would at 0.5-1 ohms but this will further reduce the already low gm, and increase required drive voltage. Remove them, do some minimal work at LMOS pairing and properly estimate the protection fuse ratings. The low and flatter gm of the LMOS helps. Here is what to do:
Measure Vgs at known current Id (make it high, 1-2A) of your LFETs, at Vgd=0 (short G and D). Select pairs so that there is least difference Vgs a pair. Within a pair, there will be a higher Vgsh, and a lower, Vgsh.
Measure current through the LMOS with Vgsh, at Vgsl. It will be lower than the one used for the initial measurement, call it Idl. Chose the worst case Idl out of all pairs (both P and N).
Find maximum current at 50V (or your chosen output stage rail voltage) on the SOA graph, using the line of your choice (DC if you want to be dead sure, 100ms if you trust your fuses to blow quickly, or somewhere inbetween), call it Imax.
Calculate maximum fuse rating as Imax * (1 + Idl/Id).
You will find that using Imax * 1.5 is a safe bet with LMOS.
Hi ilimzn,
this is maybe offtopic, but i need to ask u what is your opinion about this two preamps? Here is DL link: http://rapidshare.com/files/3222318/Preamp_s.rar.html . The same topology, but with two different implementation.
Please, can u send me your e-mail to risci@softhome.net . Imam par pitanja vezano za gore pomenute preamp-ove. Hvala.
this is maybe offtopic, but i need to ask u what is your opinion about this two preamps? Here is DL link: http://rapidshare.com/files/3222318/Preamp_s.rar.html . The same topology, but with two different implementation.
Please, can u send me your e-mail to risci@softhome.net . Imam par pitanja vezano za gore pomenute preamp-ove
. Hvala.1) Cascoding Q11 not solve my "unsymmetrical compensation problem" . When Q11 is cascoded in such way, then feedback through C7 will be in wrong phase, just like C1 connected to collector of Q12 and base Q11. So I still dont know purpose of C7.
2) I think that Q4 (the upper 2N5486) is for maintain constant drain-source voltage over Q3. In that conditions Q3 will be very good current source, immune to voltage swing.
. When Q11 is cascoded in such way, then feedback through C7 will be in wrong phase, just like C1 connected to collector of Q12 and base Q11. So I still dont know purpose of C7.2) I think that Q4 (the upper 2N5486) is for maintain constant drain-source voltage over Q3. In that conditions Q3 will be very good current source, immune to voltage swing.
wojtek5001 said:1) Cascoding Q11 not solve my "unsymmetrical compensation problem"
Yes of course, you are right. It seems I accidentally deleted the sentence where i emphasized this, when editing to cut down size to 10000 characters (it was a bit over and would not post)
Of course, one could approximate an R18 to get some measure of compensation, but as I show in the above post, there are other considerations to this.
Exactly, this is a standard cascode FET CSS. The only thing is, residual capacitance may not be ideal because the Vds of the lower FET is quite low, but I think it will be just fine for this application.
I also forgot to mention that, to an extent, utilizing a high ripple PSU to get good clipping with minimum heat penalty, does increase distortion close to clipping, due to Cgd nonlinearity of the LFET. It is slightly better than VMOS/HEXFET and a lot better than ripple feedthrough, though.
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