lumanauw wrote:
Note that not just T1 but the darlington drivers add to distortion too.
Also see post #1325
Good idea. Making the components within the PFB loop more linear is an improvement especially because PFB loops amplify their own distortion). What Bob Cordell did was to put emitter resistors, 26.1 ohms, in T1 and T2 rather than increase the current. You'll have to calculate which is better and more practical.
Note that not just T1 but the darlington drivers add to distortion too.
Also see post #1325
thanh wrote:
No one has yet suggested a definition for what "EC" is meant to be so I'm looking just at Bob's circuit and understanding what it does.
Essentially, it applies 31dB of NFB around the output FETs, with a roll-off at about 75kHz (into an 8-ohm resistive load).
To improve upon this the obvious approaches are:
1) To increase the NFB, without reducing stability
2) To improve the linearity of components in the feedback loops
3) To improve stability
There may be other approaches
Lumanauw just suggested a practical attempt at #2.
Remember, "EC" is not a new thing. It is just another feedback loop. So you can always try to design an entirely different way to implement 31dB or more of NFB that works better.
Keep the ideas coming.
The first step in improving something is to understand how it works.
No one has yet suggested a definition for what "EC" is meant to be so I'm looking just at Bob's circuit and understanding what it does.
Essentially, it applies 31dB of NFB around the output FETs, with a roll-off at about 75kHz (into an 8-ohm resistive load).
To improve upon this the obvious approaches are:
1) To increase the NFB, without reducing stability
2) To improve the linearity of components in the feedback loops
3) To improve stability
There may be other approaches
Lumanauw just suggested a practical attempt at #2.
Remember, "EC" is not a new thing. It is just another feedback loop. So you can always try to design an entirely different way to implement 31dB or more of NFB that works better.
Keep the ideas coming.
Hi, Traderbam,
I've been thinking about this too.
If we refer to HEC schematic in post #1439, the input to the EC system is from emitors of T3-T4 (via R2).
The "input" here is already distorted by the non-linearity of T3+T4 AND also by the non-linearity of the VBE multiplier itself (the input is separated by 2, taken from output of emitor of T3 and emitor of T4). As far as I know, VBE multiplier is never very rigid.
How about this : The input is taken from VAS output (not from pre-driver transistors), and to make it low impedance (to be able to drive the EC system), we add a buffer (BF) before it's entering the EC system. The BF can be diamond buffer.
This way, the input is less distorted, relatively better representating the output of the VAS (because it is entering the EC system only by 1 node, point A, instead of 2 nodes in original HEC from emitors of T3-T4).
And to power the EC system, we put CCS in collectors of Q1 and Q2.
This way Q1 and Q2 will be comparing 1 node (input=VAS output via BF) to 1 node (output node), without the distortion of VBE multiplier+distortion of pre-driver (T3-T4).
You can read my mind?
I've been thinking about this too.If we refer to HEC schematic in post #1439, the input to the EC system is from emitors of T3-T4 (via R2).
The "input" here is already distorted by the non-linearity of T3+T4 AND also by the non-linearity of the VBE multiplier itself (the input is separated by 2, taken from output of emitor of T3 and emitor of T4). As far as I know, VBE multiplier is never very rigid.
How about this : The input is taken from VAS output (not from pre-driver transistors), and to make it low impedance (to be able to drive the EC system), we add a buffer (BF) before it's entering the EC system. The BF can be diamond buffer.
This way, the input is less distorted, relatively better representating the output of the VAS (because it is entering the EC system only by 1 node, point A, instead of 2 nodes in original HEC from emitors of T3-T4).
And to power the EC system, we put CCS in collectors of Q1 and Q2.
This way Q1 and Q2 will be comparing 1 node (input=VAS output via BF) to 1 node (output node), without the distortion of VBE multiplier+distortion of pre-driver (T3-T4).
Attachments
Hi, Traderbam,
Maybe (I'm not sure), to be able to make adjustment of how much EC we want the CCT to do, we can put VR (VR1) between input and output?
Or do you have idea where to put VR to adjust how much EC we want? Because this modified CCT seems not following the original HEC equation : R2/R1=R3/(R3+R4) since R1 and R2 are missing.
Yes, that would be nice
Maybe (I'm not sure), to be able to make adjustment of how much EC we want the CCT to do, we can put VR (VR1) between input and output?
Or do you have idea where to put VR to adjust how much EC we want? Because this modified CCT seems not following the original HEC equation : R2/R1=R3/(R3+R4) since R1 and R2 are missing.
Attachments
Troublesome thought:
Take Mikeks' schematic a few posts ago and consider if one were to fry to implement pretty much as is in a real amplifier. A lot of folks consider a VI limiting circuit a requirement. As I try to visualize one added to Mikeks' example it occurs to me that when the VI limiter activates the EC circuit might "fight" it. I'm not sure about this since it's getting way too complex for my small brain.
Take Mikeks' schematic a few posts ago and consider if one were to fry to implement pretty much as is in a real amplifier. A lot of folks consider a VI limiting circuit a requirement. As I try to visualize one added to Mikeks' example it occurs to me that when the VI limiter activates the EC circuit might "fight" it. I'm not sure about this since it's getting way too complex for my small brain.
lumanauw said:
That is the modification I have made on this amplifier here:
http://www.diyaudio.com/forums/showthread.php?postid=1061760#post1061760
http://www.diyaudio.com/forums/showthread.php?postid=1061815#post1061815
And it works…
Hawksford equation
I try to figure out where the equation R2/R1=R3/(R3+R4) coming from.
I've marked A and B in the below schematic. EC will work if there is error, delta d(B-A). EC will not do anything if d(B-A)=0.
Incase of there is difference between B and A / d(B-A).
Lets see the upper side. Lets say R4=3k, R3=1k. Base of Q3 will not experience the full d(B-A) (full error), but it only experience the fraction of it, due to resistor divider effect of R4 and R3 betweeen point A and B.
In this example, the base of Q3 will only experience 25% of the error (1k/(1k+3k)). The reference is point A.
So, Q3 only experience 25% of the error. In this case the EC has to be made 1/(25%) or 4times bigger than what base of Q3 sense, in order to make full elimination of the error.
This is made by simple RC/RE amplification. For Q3, RE=R2 and RC=R1. To make 4x amplification, just set R1=4xR2.
So, we got the equation R2/R1=R3/(R3+R4).
Is what I wrote above right?
I try to figure out where the equation R2/R1=R3/(R3+R4) coming from.
I've marked A and B in the below schematic. EC will work if there is error, delta d(B-A). EC will not do anything if d(B-A)=0.
Incase of there is difference between B and A / d(B-A).
Lets see the upper side. Lets say R4=3k, R3=1k. Base of Q3 will not experience the full d(B-A) (full error), but it only experience the fraction of it, due to resistor divider effect of R4 and R3 betweeen point A and B.
In this example, the base of Q3 will only experience 25% of the error (1k/(1k+3k)). The reference is point A.
So, Q3 only experience 25% of the error. In this case the EC has to be made 1/(25%) or 4times bigger than what base of Q3 sense, in order to make full elimination of the error.
This is made by simple RC/RE amplification. For Q3, RE=R2 and RC=R1. To make 4x amplification, just set R1=4xR2.
So, we got the equation R2/R1=R3/(R3+R4).
Is what I wrote above right?
Attachments
In this modified EC, the base of Q1 still only experience a fraction of the real error, due to voltage divider effect of R3+R4.
Here, there is no RE (R2) or RC (R1), so the gain of Q1 cannot be adjusted.
But we can put another voltage divider for the input (emitor of Q1), that is R1/VR1. So we can adjust the optimum EC.
Here, there is no RE (R2) or RC (R1), so the gain of Q1 cannot be adjusted.
But we can put another voltage divider for the input (emitor of Q1), that is R1/VR1. So we can adjust the optimum EC.
Attachments
Lumanauw,
I've adopted Bob's output stage to your new circuit. I've measured the feedback gain (the "EC" power if you will). It is less than one which means it isn't doing any correcting.
The reason is that your circuit has removed the PFB loop, the one that has maximum gain when your "balance" equation is satisfied, so there isn't much gain.
What you need to think about is how to increase the gain.
Note, that in your diagram, R3 and R4 give negative feedback from both the output and point A. But you don't really want feedback from point A...because this is in front of the output transistor so this feedback is not reducing the error of the output transistor. The negative feedback from point A is actually reducing (or stealing if you like) the feedback around the output transistor.
Have a think about how you can change the design so that the feedback around the output device is increased.
Brian
I've adopted Bob's output stage to your new circuit. I've measured the feedback gain (the "EC" power if you will). It is less than one which means it isn't doing any correcting.
The reason is that your circuit has removed the PFB loop, the one that has maximum gain when your "balance" equation is satisfied, so there isn't much gain.
What you need to think about is how to increase the gain.
Note, that in your diagram, R3 and R4 give negative feedback from both the output and point A. But you don't really want feedback from point A...because this is in front of the output transistor so this feedback is not reducing the error of the output transistor. The negative feedback from point A is actually reducing (or stealing if you like) the feedback around the output transistor.
Have a think about how you can change the design so that the feedback around the output device is increased.
Brian
Hi, Traderbam,
Sorry, I missed it. This EC indeed becomes not effective, because T1 and T2 are comparing 3 points now.
1. input (from VAS to emitors of Q1-Q2),
2. output (from output node to R4), and
3. output of predriver transistor (emitor of Q3-Q4).
The sensing voltage divider (R3-R4) indeed cannot be formed by putting R3 towards emitors of predriver Q3-Q4 (for this configuration).
I'll try to make it better.
Thanks for the SIM
Sorry, I missed it. This EC indeed becomes not effective, because T1 and T2 are comparing 3 points now.
1. input (from VAS to emitors of Q1-Q2),
2. output (from output node to R4), and
3. output of predriver transistor (emitor of Q3-Q4).
The sensing voltage divider (R3-R4) indeed cannot be formed by putting R3 towards emitors of predriver Q3-Q4 (for this configuration).
I'll try to make it better.
Thanks for the SIM
Lumanauw,
The gain measured here is outside the nominal EC loop, and, therefore, tells you nothing about the performance of the circuit.
As you may have deduced from here and elsewhere, your EC transistors must have resistive loads.
These allow you to set the product of the gains across the summers to unity; you used active loads.
Moreover, defining the gain in your second summer is accomplished by emitter-degeneration of your EC BJTs; this is impossible in your circuit because of your active collector loads.
Additionally, your input to the circuit is incorrect.
The gain measured here is outside the nominal EC loop, and, therefore, tells you nothing about the performance of the circuit.
As you may have deduced from here and elsewhere, your EC transistors must have resistive loads.
These allow you to set the product of the gains across the summers to unity; you used active loads.
Moreover, defining the gain in your second summer is accomplished by emitter-degeneration of your EC BJTs; this is impossible in your circuit because of your active collector loads.
Additionally, your input to the circuit is incorrect.
Attachments
