Bob Cordell Interview: Error Correction - Page 347 - diyAudio
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Old 13th June 2008, 02:52 PM   #3461
dimitri is offline dimitri  United States
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Agreed, thanks
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Old 16th June 2008, 05:48 PM   #3462
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Quote:
Originally posted by Edmond Stuart
Hey Bob, where are you? Running out of text or still puzzled by that patent?

Hi Edmond,

Neither.

Do you miss me? :-).

Actually, I have been unbelievably busy at work the last couple weeks. I have spent what little time I have had over on the Blowtorch thread trying to contribute some constructive input on PIM.

I have not looked at the patent, but I did look at the figure you posted a few posts back. I agree that taking Miller compensation from the VAS collector node or from the following emitter follower in that particular circuit will likely disrupt the EC function.

Cheers,
Bob
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Old 16th June 2008, 07:48 PM   #3463
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Yes, I did miss you.
Anyhow, thanks for your reply
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Old 21st June 2008, 07:11 PM   #3464
CBS240 is offline CBS240  United States
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Hi

I have a question regarding Bob's hexfet output stage configuration and thermal biasing. If a single BJT can compensate both hexfets, I don't see why adding a separate Vbe multiplier like this wouldn't work. Of course, that doesn’t mean it will work. Maybe it's been discussed before but I missed it. My goal is to push the bandwidth of the EC amplifier by using small signal SMD's and minimizing trace lengths. Is this a prudent direction to take?







(compensation not included)
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Old 22nd June 2008, 06:15 AM   #3465
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Or could it work by setting the Vbe multiplier with constant conductance and use the pot to adjust the EC bias. It's not really important, just a thought.
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Old 22nd June 2008, 09:27 PM   #3466
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Quote:
Originally posted by CBS240
Hi

I have a question regarding Bob's hexfet output stage configuration and thermal biasing. If a single BJT can compensate both hexfets, I don't see why adding a separate Vbe multiplier like this wouldn't work. Of course, that doesn’t mean it will work. Maybe it's been discussed before but I missed it. My goal is to push the bandwidth of the EC amplifier by using small signal SMD's and minimizing trace lengths. Is this a prudent direction to take?

(compensation not included)

Hi CBS240,

It is a worthy goal to get the EC differential amplifier off of the heat sink and close in to the rest of its related circuitry. That was a compromise that I took in my original MOSFET EC amplifier, namely placing one of the EC differencing amplifier transistors on the heatsink to acheieve the needed temperature compensation.

I have since toyed with various ideas on how best to leave the differencing amplifier transistor off of the heatsink and achieve the necessary temperature compensation by other means, but have not seriously pursued any of those.

Cheers,
Bob
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Old 25th June 2008, 08:12 AM   #3467
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I decided to spend some otherwise idle time burning up a few brain cells on ways to eliminate the need for heat sinking the error difference amplifier transistors. IMHO this is one of those experiments that may be better to build a real circuit instead of relying on just calc and sim......

This is a quick sketch of a circuit option that seems to work correctly, for the most part. I measure a difference between points A and Vout that is consistent with what I expect to see driving the changing Vgs WRT Iout. Q: Is there any significant drawbacks for using J-fet’s for the EC difference amplifiers? If the whole amplifier DC offset is controlled by a servo, a small difference in Vgs for the P and N channel J-fet’s @ Id shouldn’t be to big of an issue as long as they are close. The J-fets' bias is around the 0 tempco Qp. I like the self-bias characteristic for this part of the circuit. If one is OK with sacrificing a few more volts, then I suppose adding a single Vbe multiplier isn’t out of the question. That part of the circuit works good giving an overall slightly negative tempco. I measured DC voltage levels with 150mA outputs’ bias using 0.1 Ohm source resistors.



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Old 25th June 2008, 08:16 AM   #3468
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some vero board and cheap parts I had lying around....
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Old 25th June 2008, 08:26 AM   #3469
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The heat sink is a bit small because I wanted to test the thermal bias reaction. As for the rest of the circuit, small is good, no?


There is some tweaking that could be done yet, but so far the results are optimistic.
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Old 26th June 2008, 08:52 AM   #3470
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Hi

Burned up a few more brain cells and reconfigured the circuit to this. The results are a bit better. There was a small instability with the J-fet circuit. It was very touchy and had the tendency to lock up and start oscillating.
The P-ch J-fet's Vgs are matched at Id; Vgs=2V. I happen to have more P-ch J-fets in the drawer than N-ch. The difference amplifier transistors bias is about 1mA. The Vbe multiplier bias is 2.6mA and still seems to create a slight overall negative tempco. I will play with this circuit some more and try to tweak it a bit better. Any tips as to what details I should concentrate on?
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