Searching the "best" CCS

[sajti]

Another idea: series RC filter between the anode of the zener to the base of the transistor. 4.7kohms+100uF means very good filtering, and slow start.

sajti

[MikeB]

Hmm, can you show schematic ? I am not sure what you mean...

Mike

[sajti]

Unfortunately no. I have no software on this PC, I use now. But it's simple: Simple RC filter between the zener, and the transistor. Series resistor, parallel capacitor

sajti

[Tim__x]

The Vas is a bigger problem in regard to PSRR. Even a fairly poor CCS in the LTP gives better rejection than a stage that is referenced to one of the rails!

[MikeB]

Tim, principally you are right. Things look a bit different for symasym...
Attached is psrr for symasym with inputstage removed. (openloop) (green = positive, red = negative)
psrr is already >40db, plus symasym's feedback of nearly 60db the psrr would easily be >100db. There are enough amps that would be happy to have 40db closed loop...
But any psrr artefact outside feedbackloop can't be compensated. Simming symasym with a virtual spice-ccs gives psrr >80db down to dc.
The negative psrr is here dominated by the ccs to the ltp, the positive can be fixed to the same level by cascoding the input devices.

Mike

[peufeu]

About the VAS vs PSRR...

Consider a standard Lin topology :

Diff pair -> current mirror -> VAS with Cdom -> buffer -> driver -> output stage.

If you wanna talk about PSRR you've got to consider where the crap coming from the power supply will enter the circuit :

* V- variations affecting the CCS biasing the input stage :
Moot point. This CCS doesn't need to sit on the V- rail ; it just needs to bias the input transistors correctly, ie. collector of CCS < diff pair tail. Just run it off a RC filtered supply from the V- rail.
Also note that this one is not corrected by feedback, but its effects should cancel if the input pair is well balanced and has a current mirror on top.

* V+ variations affecting the diff pair : it affects both transistors equally.

* V- variations affecting the VAS biasing current source : these should be corrected by feedback, if there is enough feedback at high frequencies. I'd say this one is important.

* V+ variations : the VAS sits on V+ but the major source of PSRR loss is in fact Cdom (read Self) which dominates the PSRR of the transistor and the current source below.

Again, running low-power stages (input + VAS) off RC-filtered supplies should do a lot for PSRR.

[MikeB]

peufeu, you are absolutely right, and i run my symasym frontend from RC filtered supplies. But, these filters degrade for low frequencies...

Anyway, i "solved" the problem, the question was as you pointed out, why the bias change was visible at the output. It shouldn't, as symasym runs perfectly balanced.
The solution: I replaced the input devices with jfets... Needs investigation...

Attached is actual psrr, green = +psrr, red = -psrr, nicely symetrical...

Mike

[Terry Demol]

Originally posted by MikeB
Ah yes, the ccs will be used to feed an input-LTP. In detail, i am trying to build a symasym with optimzed psrr to check the sonic advantages.

Attached is negative psrr of a symasym6, green uses standard 2-bjt-ccs, red cascoded jfet. As you can see, psrr degrades heavily below 100hz, also the normal ccs shows a resonance at 9mhz.
The peak at 13hz down shows that there is an additional problem...

As i want to publish schematic, i should avoid use of exotic parts, they would be substituted anyway.

Mike

Mike,

Some thoughts:

The bootstrapped jfet CCS is always a very good option for very
high OP Z. The bootstrapping fights against the miller capacitance
at higher frequencies which becomes + feedback.

Use gate stopper on bootsrap jfet.

All this is pretty academic anyway because which jfet has suitably
high voltage rating for this application aswell as a suitably high
vgs to allow headroom for the current setting jfet?

Stick with the bjt pair, split the 22k bias R into 2 x 11k. 100uF cap from middle of 2 x 11k to -PS rail.

Cheers

Terry

[jcx]

you seem to be confused, bootstrapping is not cascoding

in my earlier posts I show both

bootstrapping in this instance is moving the voltage of the "other" end of the current source the same as the "working" end at the diff pair emitters

This is easily done with a R divder with the same ratio as the feedback network, the bootstrap (small signal) voltage can match the diff emitter V to better than 99%, giving ~ 100x multiplcation of the ccs effective dynamic Z

my LtSpice sim doesn't use the best fets for this app, just the 1st pair I grabbed from the default part list

a real crd will get close to 10 MegOhm Dynamic Z, bootstrapping the crd would probably be sufficient for just about any requirement, cascoding and bootstrapping a crd with approprialy selectd fet would likely put ccs Z so high that pcb stray C impedance becomes the limiting factor over much of the audio band

Originally posted by jcx
R5/R4 = R2/R1 (trimmed R4 for estimated D1 Zener dynamic Z of ~ 15 Ohm)



1KHz on V4 positive supply probes probes psrr

3KHz at V3 input tests input cmrr

plot Id(J2)*1000
for same display/"units" as earlier posts, ~ 115 dB psrr, 140dB input cmrr

[Terry Demol]

Originally posted by jcx
you seem to be confused, bootstrapping is not cascoding

in my earlier posts I show both

Not so JCX.

I know and have -used-, (not simmed) both. Some bootstrapped
circuits get their origins from Hawksford.

Your example shows in fact 2 bootstraps. 1) is, as you say, the
feedback R divider forcing theoretically zero voltage swing
across the CCS. 2) is actually the 2N4393 gate connected
to the 2N5486 source.

The R divider from OP is a neat idea.

Question is, have you tried it, what does it sound like, how does it
affect -actual- performance of amp?

Cheers

Terry