Amp distortion

[zeus_threat]

Hi i've been simulating and i have built this amp. Simulation shows distortion and veroboard protoype has problems with inductive loads(x-overs, e.t.c). A 0.5uH helps but does not cure it. Can anyone help?

Thanks

 

[davidallancole]

Where are you putting the inductor? In line with the speaker? What about adding the zobel network from the speaker + to gnd?

 

[CBS240]

Hi Zeus


Try a forum search on Zobel network. It is discussed extensivly.


http://users.ece.gatech.edu/~mleach/ece4445/downloads/zobel.pdf

 

[darkfenriz]

I don't know if this is the problem, but R3 is too high. Try around 820ohms.

 

[jan.didden]

Decrease C4 to 10pF, see if that stops instability.
Sims donot take into account all kinds of parasitic caps and inductance. The map is not the world.

Jan Didden

 

[Nelson Pass]

You are going to need an RC network to ground at the output
(say .1 uF and 5 ohms) no matter what you do.

 

[davidallancole]

I agree with darkfenriz as well. R3 should be lower. Have you put an oscilloscope on the output to see if it is oscillating?

 

[zeus_threat]

simulation transient analysis

Well the inductor in series helped solved mostly but not completely the problem. Shortcircuited in parallel with a 10R resistor is worse. I'll try the 1uF from output to ground. But still my main problem is distortion i am seeing in the simulation. Anyone has any idea where its coming from? Simulation o/p attached for 20Hz and 20KHz signals.

 

[zeus_threat]

Prototype circuit

Attached is the schematic of the prototype i have built

 

[teemuk]

Looks like clipping into rails... Does that CCS for voltage amplifier stage work properly?

 

[latala]

I would have expected to see some rail decouplers at the series resistor to the vas stage about 100 uf!
Also at a glance the diff pair looks like it ill be unbalanced r3 should be around 1 k r3 should be aprox two times the value of the constant current tail resistor with that type of CCS
Also i can not see to clearly but it looks like rail clipping with rail sag combined ie the droops between rectifier charging pulses on the psu
Regards Trev

 

[davidallancole]

Try changing R3 like has been mentioned before. You are way over biasing Q3 with your R3 value. You need only ~0.7V to turn Q3 on and you are looking at closer to 2.2V with what you have shown. Drop the resistor down to like 680 to 1K.

 

[CBS240]

Looks like Q9 bias 1.2V/330R=3.6mA. 0.6V/(3.6/2)=330R.

IMO, there should be a resistor on the base of Q10 in case Q10 saturates it won't change the bias of Q9. Or better yet another set of diodes and resistor to separate them.

 

[powerbecker]

Re: simulation transient analysis

....... But still my main problem is distortion i am seeing in the simulation. Anyone has any idea where its coming from? Simulation o/p attached for 20Hz and 20KHz signals. [/B]

Hello Zeus,

for me looks like that your timestep is far too big.
Perhaps You use automatically generated timesteps :
switch this off and use much smaller steps.

Regards
Heinz!

 

[zeus_threat]

Better simulation results

I modified the amp with values shown. I'll post the transient analysis next, but reducing the timestep to 100mS for 20Hz and 100uS for 20KHz did not show any distortion. Is this reliable? I mean not for real world but at least for the simulation?

Thanks

 

[zeus_threat]

The transient analysis looks better

Attached are the transient analysis with reduced time steps. Increasing the timestep even with R3=1K shows distortion. Any particular reason? Am using simetrix intro could it be due to the fact that its an intro version?

 

[davidallancole]

I would try using an ac voltage source in the similation that has the same peak voltage. Check it against your output signal and you will see if it strays from the signal much.

 

[AndrewT]

Hi Zeus,
I think powerbecker has hit it with

for me looks like that your timestep is far too big. Perhaps You use automatically generated timesteps :
switch this off and use much smaller steps.

Have you found how to do this?

R3 is still too big.

Q3 Vbe controls the current in r3. So 0.6V pushes 0.6mA through R3 (0.6/1000).
Your constant current sink is set at 2mA (0.7/330) so you are sinking 1.4mA through Q2. That makes your LTP unbalanced. That in turn increases distortion in the LTP.

You must alter some or one of your resistors to balance the currents in the LTP halves. You can monitor the currents in R1 & R2 to check balance.

 

[MikeB]

You must reduce C5 in size, 100pF here is nearly a guarantee for stability problems. Try 10pF or 22pF at most.
The purpose of this c is to phasehift the feedback signal, but unfortunately it also decreases closed loop gain for higher freqs, increasing feedback factor. Values like 100pf here can only be used for amps that are unitygain stable.

Mike

 

[CBS240]

R3 is still too big.

Q3 Vbe controls the current in r3. So 0.6V pushes 0.6mA through R3 (0.6/1000).
Your constant current sink is set at 2mA (0.7/330) so you are sinking 1.4mA through Q2. That makes your LTP unbalanced. That in turn increases distortion in the LTP.

You must alter some or one of your resistors to balance the currents in the LTP halves. You can monitor the currents in R1 & R2 to check balance.

oopps I miscalculated post 13, I didn't take into account it is a simulator. Real small signal BJT's Vbe is usually around 0.6V.

(1.4/330)/2=2.12mA 0.7/2.12=330R...not counting base current of Q3. Having 2 diode drops on the CCS of the LTP, makes R3 equal in value to R16 since the current is divided equally as Andrew stated. Each transistor needs to have equal heat dissapation or drift will occur (well in the real world it will )