Calculating VAS current for mosfet output

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1. How to calculate vas current for the mosfet output stage?
2. What are the differences in calculations when driving mosfets from the vas stage,directly, and when driving with bjt buffer stage?
3. Anyone tried to experiment the sound quality of normal biased vas stage versus overbiase vas stage?

Thanks!
 
mosfet outputs require surprizing amounts of current drive at higher frequencies due to gate capacitances

source followers don't completely bootstrap the Cgs and you always see all of the Cgd

a point that i think can be seen in http://www.ne.jp/asahi/evo/amp/J200K1529/report.htm going from fig 7 to fig 13 (lots of mods but i think the performance couldn't get near these levels without the buffering of the output fet gate impedance)
 
I discovered that higher VAS stage bias(only tried in simulations), gives lower distortion on high freq. I tried it in several circuit designs and vas stage bias 50mA at 10KHz, gives 0.2%THD and 10mA at 10KHz, VAS iddle curent gives 1.5%THD. THis is extermly BAD and i dont know is it about the simulation software? I triad several standard designs and I had same pour THD levels...
I use SIMETRIX software for simulation.
The same circuits had very good THD for 1KHz (up to 0.0025%THD).

HELP!

I dont have osciloscope or THD meter to try it in practice...
 
bogdan_borko said:
I discovered that higher VAS stage bias(only tried in simulations), gives lower distortion on high freq.

Yes, this is normal because the MOSFETs are a capacitive load, so load increases with frequency.

I tried it in several circuit designs and vas stage bias 50mA at 10KHz, gives 0.2%THD and 10mA at 10KHz, VAS iddle curent gives 1.5%THD. THis is extermly BAD and i dont know is it about the simulation software? I triad several standard designs and I had same poor THD levels...
I use SIMETRIX software for simulation.
The same circuits had very good THD for 1KHz (up to 0.0025%THD).

There is something odd going on, as for small signals (well below the power rails) the MOSFET Cgd is fairly linear. This would mean that the open loop gain decreases 10x from 1k to 10k, distortion should increase by the same amount.
Make sure your output stage is biased properly!!! If not, there is a large discontinuity in tge MOSFET transconductance, where it drops at crossover, resulting in lowering the 'bootstraping' action for Cgs, which is often up to an order of magnitude higher than Cgd, so current demand on the VAS suddenly increases. At higher frequencies this crossover phenomenon takes a larger 'angle' out of the sinusoidal, therefore increasing distortion far beyond whet a mere capacitance at the VAS output would.

In order to check this, you may want to sheck the waveform of the current flowing into the MOSFET gates in your simulation.
 
bogdan_borko said:
anyone to answer my question?
It`s not japanese amps thread!!!

JCX gave most of the answer in post #2. One thing to consider is that vertical MOSFET output devices have a much higher Cgd (and much more non-linear as well) than do lateral devices. So you need to tell us which output devices you are planning to use and also the configuration (eg, source-follower).
 
Upupa Epops said:
Good analysis of this question make years ago Erno Borbelly in The Audio Amateur at paper about his 60 W mosfet amp...I don't remember, which number it was ( maybe half of 80's )....

Actually, Erno's analysis in that article was severely flawed. He included Cgs of the output devices in his calculations. As JCX notes in post #2, most of Cgs is bootstrapped and does not affect the driver stage.
 
I would like to note that all the PSpice-based MOSFET models that I have seen to the date use plain linear capacitances, thus yielding any THD analysis useless. Furthermore, the MOSFET model system built into PSpice only supports constant capacitances, so modelling real device behaviour is a potential nightmare.

Might SIMetrix be employing non-linear capacitances and showing the truth about MOSFET stages? :D (Then again, who could have expected low THD from devices that require plenty of quadratic and exponential laws in order to be characterized with equations?)
 
bogdan_borko said:
1. How to calculate vas current for the mosfet output stage?
2. What are the differences in calculations when driving mosfets from the vas stage,directly, and when driving with bjt buffer stage?
3. Anyone tried to experiment the sound quality of normal biased vas stage versus overbiase vas stage?

Thanks!


1. There are many issues here. If vas can work in class AB like in crescendo the vas bias can be lower. First to calculate is gate current for desired slew rate. Robert Cordell did it and got 17mA for 100V/us, Cgs=700pF, Cgd=100pF in source follower mode.
It is worth noting here, that greater bias of output stage and therefore higher output transconductance also reduces gate current.

2. Hfe

3. Try to contact a member: Sajti .A s far as I remember he did some experiments with mosfets driven directly from vas and got best results with 80mA or so( ?!) , much current for sure.

best regards
 
UPUPA EPOPS
---Good analysis of this question make years ago Erno Borbelly in The Audio Amateur at paper about his 60 W mosfet amp...I don't remember, which number it was ( maybe half of 80's )....---

In his 120W 8 Ohm amplifier using 2 Hitachi Mosfet devices per polarity, published in march 1983 in Wireless World, Boberly discussed the VAS current. He was assuming 150 pF each for the Mosfets, and 400 pF Ccomp, for a whole input capacitance around 1 nF. For a slew-rate of 100 V/µS. he calculated 100 mA. He ended with 50 mA in the real amplifier.
 
nip
 

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Bootstraping Cgs

Here is the mosfet Cgs in source follower mode model, ovesimplified , with SE work and purely resistive load and without Cgd.
However showing bootstraping dependancy on load impedance and transconductance.
If mosfet is highly biased, the gate charging current gets very low and makes a mosfet nearly perfect device. Mosfet lovers know it very well.
Assuming 1/10 of Cgs is bootstraped is just first approximation I think.
 

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