Simple Killer Amp - Circuit analysis

[Eva]

Originally posted by Terry Demol


1) The OP MOSFET is driven by a high beta high Ft BJT follower.
The followers job is to address the highly non linear capacitive load
of the MOS. Looking into the IP of the follower you will see virtually
NONE of this highly reactive load and it will handle the load easily
provided the right device (bjt) is chosen.

Come on, is it so hard to understand that the LTP has to provide exactly the gate drive current divided by the beta of the buffer, with all its non-linearity and its reactivity? Note that such a high-FT transistor will have a beta of 100 to 200.

Is it so hard to understand that the voltage drop caused by this drive current across the LTP degeneration resistors, amplified by the OL gain, will appear as a new signal superimposed to the output voltage? That's a clever way to "listen to the gates".

Also, since the gates are driven with differential currents I_bias=I_upper+I_lower, the designer relied in both banks of MOSFETs having the same constant input capacitance for bias stability in dynamic conditions (playing). But these capacitances are not equal, nor constant at all. In other words, the circuit is so badly designed that it can't even keep bias under control. Simulation won't show it because most models use constant capacitances.

[lineup]

What circuit is this about.
7/10 would not know this by heart, Eva.
Give us some little background info, please.

thanks

[jacco vermeulen]

The post reads "simple killer amp'' on the top, GB150.

Eva, thanks for the holiday.

[hifryer]

Well Eva,

This is the slippery slope of designing with sand!

Two schools:

1. design in globs and globs of gain and then fix all ills with global NFB.

2. make the most "perfect design" by band-aid over band-aid and end up with more and more complexity contributing more and more subtle issues. None of the fixes work as the same non linear devices are used in each fix. Of course models make it all look perfect as the models are purile. So still add heaps of NFB anyway.

regardless of which course used, such amplifiers will never entirely disappear.

A better solution is to use those hot old fashioned intrinsically more linear devices ;-)

but sand IS CHEAP!!!

cheers,

[Eva]

This is the circuit:



And this picture of a completed module supplies a bit more information about component values and the current sources:




jacco vermeulen:

With pleasure!


hifryer:

Virtue is in the middle

[tschrama]

schematic?

lol posted just at the same second i guess

[AKSA]

Let us assume 2nF per mosfet. As remarked, this figure varies somewhat with dynamic channel conditions, but it will do for starters.

As a rough approximation this is an impedance of 2K per mosfet pair at 20KHz. We can thus assume a capacitive reactance of 2K to AC ground must be fed by the bipolar EF.

The AC at the gates is not a large signal, because the output mosfets are in common souce.

I do not know how much degeneration GB is using; assume 0.22R. We could posit a signal at this point of around 3.5V peak. This would be a very high estimate, and would give close on a combined 10A swing per rail at least for a transconductance of 5S, a typical figure for these devices.

So we need around 1.75mA peak of charge/discharge current for the gates. If EF current is around 10mA - and it must be stressed these values are not known because the working schematic is not published - this can be met with ease, though there will be a small EF Vbe variation. The gate resistor will also modulate the drive markedly. In truth the demand from the LTP side of the EF would not be more than 1/100th (beta) of this; assume an AC current therefore of 17.5uA. This is trivial; LTP stage current would be at least 1mA and likely 2mA, so up to 30% or so of 1000uA could be readily available.

Most mosfet amps are common drain, follower designs; so the gate drive is not so tricky. However, in the past I once drove a pair of mosfets in SE with only 4.2mA of stage current on a CFP configuration; response was only 3dB down at 75KHz.

It is true there will be non-linear modulation of the mosfet gates due to current starvation at the peaks, but it will easily be accommodated by the huge feedback factor of this design.

The stated intention of the designer has been to reduce distortion to vanishingly low levels; with high speed and no formal VAS this has been achieved with feedback. I have always disagreed with this approach - the so-called 'straight wire with gain', but I believe the stated design goal is achieved here and from an engineering POV this design is better than most.

It is NOT therefore a bad design, certainly not deserving of high derision, and to degenerate this thread narrowly to a mere engineering discussion ignores the spirit of the previous thread where the criticism appeared, which is 'Listening Impressions'.

I suggest, Eva, you stop winding people up by attacking a design on spurious grounds, particularly when the designer cannot defend himself.

Cheers,

Hugh

[macka]

Originally posted by Eva
This is the circuit:



And this picture of a completed module supplies a bit more information about component values and the current sources:




jacco vermeulen:

With pleasure!


hifryer:

Virtue is in the middle

Eva,

Your not in possession of the facts (the actual schematic)?

As the design is Greg Ball's IP he has chosen not to fully disclose it publicly and it is therefore reasonable to assume he has not provided a full explanation of his design.

If you were in possession of the full schematic its doubtful you would bother posting.

The problem is without the facts you don't know what your talking about..Do you!

[Eva]

AKSA:

Lets consider some lateral output device, a Toshiba 2SK1529 (180V 10A) for example. The funny part here is that the transconductance sweeps from less than 0.4 S at 50mA Id (bias level) to more than 5S at 10A (maximum peak output current).

The input capacitance sweeps from 2nF at clipping to 500pF or so when the other rail clips. Furthermore, the reverse transfer capacitance also sweeps between 1nF (!!!) at clipping and a few picofarads when clipping to the other rail.

Thus, these gates cannot be analysed as simple 2nF capacitors because the drive current waveform is very complex.

Also, note that this design relies strongly on constant gate input capacitance, equal for both banks of output devices, for keeping bias properly, but it isn't. Do you understand the complementary-gate-currents principle employed?

Concerning drain resistors and degeneration, both the schematic and the board tell that there isn't any. Lateral MOSFETs doesn't require that anyway.

p.s.: I have tried the self-bootstrapped emitter gate-drive tecnhique that the author has patented, but I have discarded it because it (obviously!) forces the bias level of the previous stage to be proportional to the average gate voltage of the MOSFET driven, which is fully dependen on the signal played and almost unpredictable. In turn, this will cause each LTP to run with unbalanced currents most of the time A classic current source or current mirror solves the problem.

[AKSA]

Eva,

From half a nF to 2nF would appear to me to be easier to drive than a consistent 2nF. And the complementarity would alternate; high one side, low the other. Since the dynamic resistance of the shared EF tail resistor would be affected by this, then we have only to ensure that there is an adequate voltage dropped between the EF emitters. There is, in fact, almost twice the rail voltage across this shared resistor so this should be adequate to ensure driving impedance is close to the 26/mA predicted as Zout by an emitter follower. For 10 mA (and I'm only guessing at the current selected, this would appear about right), this means that source impedance is around 2.6R, which would appear to be dwarfed by the value of the gate resistor.

I think you are probably right about a lack of bias control, particularly at high frequencies. Yet I understand that this design does not cross-conduct, but perhaps we should ask the advice of others who know the circuit. Certainly this would be the problem if there was a lack of bias control.

I may be wrong, but I believe GB is using IRF hexfets.

R19-22 is source degeneration clearly marked on the schematic. Why do you think there is no degeneration on the OP mosfets when clearly there is?

A classic current mirror will still run unbalanced at the LTP unless special provision is made for the bias current of the EF by using asymmetrical degeneration.

As Terry remarks, bias control would be tetchy at best with a current mirror. As mentioned, the only criticism I make of this circuit is the size of the bootstrap cap on the EF/LTP; judging from the picture I would say this cap is not much more than 220uF and for adequate bootstrap action with only 1.3V of pd to play with I would suggest something closer to 2,200uF. Alternatively, it could be scaled down and cross coupled to the opposite EF.

Frankly, I don't see the point of this debate any more. You have your POV, I have mine. Rather than carp like a couple of weary academics let's call it off.

Cheers,

Hugh