Terry Demol said:
Come on, is it so hard to understand that the LTP has to provide exactly the gate drive current divided by the beta of the buffer, with all its non-linearity and its reactivity? Note that such a high-FT transistor will have a beta of 100 to 200.
Is it so hard to understand that the voltage drop caused by this drive current across the LTP degeneration resistors, amplified by the OL gain, will appear as a new signal superimposed to the output voltage? That's a clever way to "listen to the gates".
Also, since the gates are driven with differential currents I_bias=I_upper+I_lower, the designer relied in both banks of MOSFETs having the same constant input capacitance for bias stability in dynamic conditions (playing). But these capacitances are not equal, nor constant at all. In other words, the circuit is so badly designed that it can't even keep bias under control. Simulation won't show it because most models use constant capacitances.
Well Eva,
This is the slippery slope of designing with sand!
Two schools:
1. design in globs and globs of gain and then fix all ills with global NFB.
2. make the most "perfect design" by band-aid over band-aid and end up with more and more complexity contributing more and more subtle issues. None of the fixes work as the same non linear devices are used in each fix. Of course models make it all look perfect as the models are purile. So still add heaps of NFB anyway.
regardless of which course used, such amplifiers will never entirely disappear.
A better solution is to use those hot old fashioned intrinsically more linear devices ;-)
but sand IS CHEAP!!!
cheers,
This is the slippery slope of designing with sand!
Two schools:
1. design in globs and globs of gain and then fix all ills with global NFB.
2. make the most "perfect design" by band-aid over band-aid and end up with more and more complexity contributing more and more subtle issues. None of the fixes work as the same non linear devices are used in each fix. Of course models make it all look perfect as the models are purile. So still add heaps of NFB anyway.
regardless of which course used, such amplifiers will never entirely disappear.
A better solution is to use those hot old fashioned intrinsically more linear devices ;-)
but sand IS CHEAP!!!
cheers,
This is the circuit:
And this picture of a completed module supplies a bit more information about component values and the current sources:
jacco vermeulen:
With pleasure!
hifryer:
Virtue is in the middle
An externally hosted image should be here but it was not working when we last tested it.
And this picture of a completed module supplies a bit more information about component values and the current sources:
An externally hosted image should be here but it was not working when we last tested it.
jacco vermeulen:
With pleasure!
hifryer:
Virtue is in the middle
Let us assume 2nF per mosfet. As remarked, this figure varies somewhat with dynamic channel conditions, but it will do for starters.
As a rough approximation this is an impedance of 2K per mosfet pair at 20KHz. We can thus assume a capacitive reactance of 2K to AC ground must be fed by the bipolar EF.
The AC at the gates is not a large signal, because the output mosfets are in common souce.
I do not know how much degeneration GB is using; assume 0.22R. We could posit a signal at this point of around 3.5V peak. This would be a very high estimate, and would give close on a combined 10A swing per rail at least for a transconductance of 5S, a typical figure for these devices.
So we need around 1.75mA peak of charge/discharge current for the gates. If EF current is around 10mA - and it must be stressed these values are not known because the working schematic is not published - this can be met with ease, though there will be a small EF Vbe variation. The gate resistor will also modulate the drive markedly. In truth the demand from the LTP side of the EF would not be more than 1/100th (beta) of this; assume an AC current therefore of 17.5uA. This is trivial; LTP stage current would be at least 1mA and likely 2mA, so up to 30% or so of 1000uA could be readily available.
Most mosfet amps are common drain, follower designs; so the gate drive is not so tricky. However, in the past I once drove a pair of mosfets in SE with only 4.2mA of stage current on a CFP configuration; response was only 3dB down at 75KHz.
It is true there will be non-linear modulation of the mosfet gates due to current starvation at the peaks, but it will easily be accommodated by the huge feedback factor of this design.
The stated intention of the designer has been to reduce distortion to vanishingly low levels; with high speed and no formal VAS this has been achieved with feedback. I have always disagreed with this approach - the so-called 'straight wire with gain', but I believe the stated design goal is achieved here and from an engineering POV this design is better than most.
It is NOT therefore a bad design, certainly not deserving of high derision, and to degenerate this thread narrowly to a mere engineering discussion ignores the spirit of the previous thread where the criticism appeared, which is 'Listening Impressions'.
I suggest, Eva, you stop winding people up by attacking a design on spurious grounds, particularly when the designer cannot defend himself.
Cheers,
Hugh
As a rough approximation this is an impedance of 2K per mosfet pair at 20KHz. We can thus assume a capacitive reactance of 2K to AC ground must be fed by the bipolar EF.
The AC at the gates is not a large signal, because the output mosfets are in common souce.
I do not know how much degeneration GB is using; assume 0.22R. We could posit a signal at this point of around 3.5V peak. This would be a very high estimate, and would give close on a combined 10A swing per rail at least for a transconductance of 5S, a typical figure for these devices.
So we need around 1.75mA peak of charge/discharge current for the gates. If EF current is around 10mA - and it must be stressed these values are not known because the working schematic is not published - this can be met with ease, though there will be a small EF Vbe variation. The gate resistor will also modulate the drive markedly. In truth the demand from the LTP side of the EF would not be more than 1/100th (beta) of this; assume an AC current therefore of 17.5uA. This is trivial; LTP stage current would be at least 1mA and likely 2mA, so up to 30% or so of 1000uA could be readily available.
Most mosfet amps are common drain, follower designs; so the gate drive is not so tricky. However, in the past I once drove a pair of mosfets in SE with only 4.2mA of stage current on a CFP configuration; response was only 3dB down at 75KHz.
It is true there will be non-linear modulation of the mosfet gates due to current starvation at the peaks, but it will easily be accommodated by the huge feedback factor of this design.
The stated intention of the designer has been to reduce distortion to vanishingly low levels; with high speed and no formal VAS this has been achieved with feedback. I have always disagreed with this approach - the so-called 'straight wire with gain', but I believe the stated design goal is achieved here and from an engineering POV this design is better than most.
It is NOT therefore a bad design, certainly not deserving of high derision, and to degenerate this thread narrowly to a mere engineering discussion ignores the spirit of the previous thread where the criticism appeared, which is 'Listening Impressions'.
I suggest, Eva, you stop winding people up by attacking a design on spurious grounds, particularly when the designer cannot defend himself.
Cheers,
Hugh
Eva said:This is the circuit:
An externally hosted image should be here but it was not working when we last tested it.
And this picture of a completed module supplies a bit more information about component values and the current sources:
An externally hosted image should be here but it was not working when we last tested it.
jacco vermeulen:
With pleasure!
hifryer:
Virtue is in the middle
Eva,
Your not in possession of the facts (the actual schematic)?
As the design is Greg Ball's IP he has chosen not to fully disclose it publicly and it is therefore reasonable to assume he has not provided a full explanation of his design.
If you were in possession of the full schematic its doubtful you would bother posting.
The problem is without the facts you don't know what your talking about..Do you!
AKSA:
Lets consider some lateral output device, a Toshiba 2SK1529 (180V 10A) for example. The funny part here is that the transconductance sweeps from less than 0.4 S at 50mA Id (bias level) to more than 5S at 10A (maximum peak output current).
The input capacitance sweeps from 2nF at clipping to 500pF or so when the other rail clips. Furthermore, the reverse transfer capacitance also sweeps between 1nF (!!!) at clipping and a few picofarads when clipping to the other rail.
Thus, these gates cannot be analysed as simple 2nF capacitors because the drive current waveform is very complex.
Also, note that this design relies strongly on constant gate input capacitance, equal for both banks of output devices, for keeping bias properly, but it isn't. Do you understand the complementary-gate-currents principle employed?
Concerning drain resistors and degeneration, both the schematic and the board tell that there isn't any. Lateral MOSFETs doesn't require that anyway.
p.s.: I have tried the self-bootstrapped emitter gate-drive tecnhique that the author has patented, but I have discarded it because it (obviously!) forces the bias level of the previous stage to be proportional to the average gate voltage of the MOSFET driven, which is fully dependen on the signal played and almost unpredictable. In turn, this will cause each LTP to run with unbalanced currents most of the time A classic current source or current mirror solves the problem.
Lets consider some lateral output device, a Toshiba 2SK1529 (180V 10A) for example. The funny part here is that the transconductance sweeps from less than 0.4 S at 50mA Id (bias level) to more than 5S at 10A (maximum peak output current).
The input capacitance sweeps from 2nF at clipping to 500pF or so when the other rail clips. Furthermore, the reverse transfer capacitance also sweeps between 1nF (!!!) at clipping and a few picofarads when clipping to the other rail.
Thus, these gates cannot be analysed as simple 2nF capacitors because the drive current waveform is very complex.
Also, note that this design relies strongly on constant gate input capacitance, equal for both banks of output devices, for keeping bias properly, but it isn't. Do you understand the complementary-gate-currents principle employed?
Concerning drain resistors and degeneration, both the schematic and the board tell that there isn't any. Lateral MOSFETs doesn't require that anyway.
p.s.: I have tried the self-bootstrapped emitter gate-drive tecnhique that the author has patented, but I have discarded it because it (obviously!) forces the bias level of the previous stage to be proportional to the average gate voltage of the MOSFET driven, which is fully dependen on the signal played and almost unpredictable. In turn, this will cause each LTP to run with unbalanced currents most of the time
A classic current source or current mirror solves the problem.
Eva,
From half a nF to 2nF would appear to me to be easier to drive than a consistent 2nF. And the complementarity would alternate; high one side, low the other. Since the dynamic resistance of the shared EF tail resistor would be affected by this, then we have only to ensure that there is an adequate voltage dropped between the EF emitters. There is, in fact, almost twice the rail voltage across this shared resistor so this should be adequate to ensure driving impedance is close to the 26/mA predicted as Zout by an emitter follower. For 10 mA (and I'm only guessing at the current selected, this would appear about right), this means that source impedance is around 2.6R, which would appear to be dwarfed by the value of the gate resistor.
I think you are probably right about a lack of bias control, particularly at high frequencies. Yet I understand that this design does not cross-conduct, but perhaps we should ask the advice of others who know the circuit. Certainly this would be the problem if there was a lack of bias control.
I may be wrong, but I believe GB is using IRF hexfets.
R19-22 is source degeneration clearly marked on the schematic. Why do you think there is no degeneration on the OP mosfets when clearly there is?
A classic current mirror will still run unbalanced at the LTP unless special provision is made for the bias current of the EF by using asymmetrical degeneration.
As Terry remarks, bias control would be tetchy at best with a current mirror. As mentioned, the only criticism I make of this circuit is the size of the bootstrap cap on the EF/LTP; judging from the picture I would say this cap is not much more than 220uF and for adequate bootstrap action with only 1.3V of pd to play with I would suggest something closer to 2,200uF. Alternatively, it could be scaled down and cross coupled to the opposite EF.
Frankly, I don't see the point of this debate any more. You have your POV, I have mine. Rather than carp like a couple of weary academics let's call it off.
Cheers,
Hugh
From half a nF to 2nF would appear to me to be easier to drive than a consistent 2nF. And the complementarity would alternate; high one side, low the other. Since the dynamic resistance of the shared EF tail resistor would be affected by this, then we have only to ensure that there is an adequate voltage dropped between the EF emitters. There is, in fact, almost twice the rail voltage across this shared resistor so this should be adequate to ensure driving impedance is close to the 26/mA predicted as Zout by an emitter follower. For 10 mA (and I'm only guessing at the current selected, this would appear about right), this means that source impedance is around 2.6R, which would appear to be dwarfed by the value of the gate resistor.
I think you are probably right about a lack of bias control, particularly at high frequencies. Yet I understand that this design does not cross-conduct, but perhaps we should ask the advice of others who know the circuit. Certainly this would be the problem if there was a lack of bias control.
I may be wrong, but I believe GB is using IRF hexfets.
R19-22 is source degeneration clearly marked on the schematic. Why do you think there is no degeneration on the OP mosfets when clearly there is?
A classic current mirror will still run unbalanced at the LTP unless special provision is made for the bias current of the EF by using asymmetrical degeneration.
As Terry remarks, bias control would be tetchy at best with a current mirror. As mentioned, the only criticism I make of this circuit is the size of the bootstrap cap on the EF/LTP; judging from the picture I would say this cap is not much more than 220uF and for adequate bootstrap action with only 1.3V of pd to play with I would suggest something closer to 2,200uF. Alternatively, it could be scaled down and cross coupled to the opposite EF.
Frankly, I don't see the point of this debate any more. You have your POV, I have mine. Rather than carp like a couple of weary academics let's call it off.
Cheers,
Hugh
Here's a couple of comments from Greg:
I generally appreciate your comments on the amp design. Just to clarify a couple of points.
The bootstrap C's have roughly 2.1V DC across them and are driving a 3K load to the rails with 2Vrms from a 7.5mA current source, so are under no compromise and even the small values used are good down to 5Hz. The bootstrapping positive feedback greatly enhances both the linearity and gain of the LTP before global feedback, whose main task is MOSFET non-linearity containment - honed to < 0.005% 2HD at moderate average levels.
The output MOSFET pole is well isolated from the dominant input stage pole as you suggest and actually becomes increasingly well defined with moderate capacitative loading. Such loading reduces OL gain as fast as increasing phase shift, maintaining generally good stability.
Thanks
I generally appreciate your comments on the amp design. Just to clarify a couple of points.
The bootstrap C's have roughly 2.1V DC across them and are driving a 3K load to the rails with 2Vrms from a 7.5mA current source, so are under no compromise and even the small values used are good down to 5Hz. The bootstrapping positive feedback greatly enhances both the linearity and gain of the LTP before global feedback, whose main task is MOSFET non-linearity containment - honed to < 0.005% 2HD at moderate average levels.
The output MOSFET pole is well isolated from the dominant input stage pole as you suggest and actually becomes increasingly well defined with moderate capacitative loading. Such loading reduces OL gain as fast as increasing phase shift, maintaining generally good stability.
Thanks
Macka,
i don't quite understand why you get so worked up for ?
Eva is stating the facts, the inherent flaws of vertical mosfets are likely to be transposed back to the LTP.
This design depends on high feedback, but it's always been clear which corner Mr Ball is coming from, he has made plenty of references to his 80s GB1 design.
imo, this design is mostly good for Class A use, and that overshoots Mr Ball's main target. But the taste is in the trying, i'm laying the boards out for 50 in A. You can't blame Eva for talking from her engineering corner.
i don't quite understand why you get so worked up for ?
Eva is stating the facts, the inherent flaws of vertical mosfets are likely to be transposed back to the LTP.
This design depends on high feedback, but it's always been clear which corner Mr Ball is coming from, he has made plenty of references to his 80s GB1 design.
imo, this design is mostly good for Class A use, and that overshoots Mr Ball's main target. But the taste is in the trying, i'm laying the boards out for 50 in A. You can't blame Eva for talking from her engineering corner.
jacco vermeulen said:
I've tried the class A config Jacco and the only difference that I was certain I could hear was in the bass range. More solid with class A. I thought that it would definitely offer improvements but the extent that it did was just not worth the extra 'sinking+heat+power.
I left one module AB and just biased up another to 1.75v reach 50w class A as per Gregs instructions. They run extremely warm though compared to AB.
When I get a chance I may try the bootstrap cap for fun but turning the SKA into class A is very easy and as long as you swap out the torroids (I used the 25-0-25v) and have a half decent heatsink then you can try it out.
jacco vermeulen said:
I'm also considering building my own version of the circuit in order to measure the actual non-linear currents and be able to post waveforms directly from my oscilloscope. Unfortunately, I'm currently working in another MOSFET based and more complex project that achieves low distortion even without feedback or high bias currents
(check the Reinventing the N-channel thread).There is no doubt that the SKA circuit will behave much better when biased into full class-A so that both sets of MOSFETs could show all their transconductance all the time. Indeed, this circuit biased into class A resembles a lot to the classic JLH (it's a bare MOSFET copy!!), but class AB or B biasing is a no-no.
The online GB150 schematic has been probably changed to include source resistors, but the GB300 one still does not show them:
As I'm linking directly to the website, any update may cause the new pictures to contradict my statements. I also remember lateral devices mentioned in that website, but I can no longer find the text. Since the boards neither showed source resistors, it maked sense to think about lateral devices (the resistors may be surface soldered in the back side, though).
An externally hosted image should be here but it was not working when we last tested it.
As I'm linking directly to the website, any update may cause the new pictures to contradict my statements. I also remember lateral devices mentioned in that website, but I can no longer find the text. Since the boards neither showed source resistors, it maked sense to think about lateral devices (the resistors may be surface soldered in the back side, though).
macka said:
Hi Macka,
So before I launch into some kind of analysis of this circuit,
I take it you are saying that there are significant differences
from modules to what is above and we don't know the 'full picture'.
I don't expect any disclosure of details here, but I take it you
are saying we are chasing our tails working with this
schematic?
And FWIW what IS the status of this circuit? There was talk of
patents, but it has been published so obviously whatever is
patentable has not been shown to us.
Sounds like Greg is holding a few cards up his sleeve?
So good luck to him.
Cheers,
Terry
Eva said:
Eva,
The GB150 schematic I have in the constructors guide is different to the one on Gregs website.
Not knowing zip about this sort of thing I can't comment on these things. However there are differences, so talk about the schematic you've posted probably isn't completely valid - to what extent I don't know.
You can take a look at the picture of the GB150 board and see for yourself what kind of parts are lacking or added compared to the schematic. Skip gate and source-drain protecting diodes and zeners.
Elementary, dear Dr Watson !
If such a circuit has flaws and depends on high feedback to behave, where would you expect something added ?
With the GB150D instructions in front of me i still can not imagine this circuit to behave in the upper frequency range.
(the GB150 is going on amp killer Quads= AKQ ?)
Elementary, dear Dr Watson !
If such a circuit has flaws and depends on high feedback to behave, where would you expect something added ?
With the GB150D instructions in front of me i still can not imagine this circuit to behave in the upper frequency range.
(the GB150 is going on amp killer Quads= AKQ ?)
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