Question for all mighty ILIMZN and others...
Hi. This is my finall design, so does anyone has any proposition before i start to build it?
1. I raised diff. stage current to 3.5mA per device, the higher idle current, better slew rate, isn`t that right?
So why in all classic designes, the diff.pair idle current`s 500uA to 1.5mA max??? The devices I`m gonna use (BC550) in this case could go even higher than 3.5mA...
2. Where should I connect hf compensation capacitors in vas stage Q9/Q10 base-emmiter?
3. The idle current of output mosfets is set to 100mA any suggestions?
4. Does anyone have spice model for BF872, I`d like to use them in vas stage instead BF471/472.
THank you ALL in advance!
I also prefer using more current in input stage.
Somwhere between 2-5 mA in each transistor.
Sometimes this can create DC-offset problems, as there is higher input bias current.
But in your case, with 2 symmetrical diff input pairs
and the use of C9 - DC-blocking capacitor in feedback
this will be no problem.
In fact, you maybe even will be able to remove C9 without any offset problem.
As far as I know, BF471/472 is very much the same as BF871/872.
They are used as cascodes in your circuit,
so I think any simulation result will be just the same.
Here is a Philips spice model of BF871:
I leave the rest of questions for other to answer.
Finally, I think you have learned a lot and your circuit looks very good, to me!
Good working, bogdan_borko!
There are some parameters that increase as bias current is increased:
- Differential gain of the LTP (check for instability).
- Current noise.
- Offset (due to higher base currents).
I would consider using MJE340/350 instead of BF471/472.
I think they would work just as good.
MJE340/350 are 300 Volt transistors in TO-126 case.
... and much much easier to find
is there eny other bc transistor with lower noise then bc550/560?
Stick with BF471/472, they will performe excelent in your circuit, lose cascode Q7/8 with BC550/560, they cannot withstand 15mA without trouble, or convert circuit into folded cascode with new biasing aragement (similar to yours), put RF blocking cap in parallel with R2 like 100p, put trimer in one of diff. pair to control DC offset or include servo that will control current betwen R10/12.
Re: Question for all mighty ILIMZN and others...
What about , a bipolar driver for driving the output Mosfets, they help to isolate the non linear input capacitance of the mosfets , from the high output impedance , cascode VAS...
Ah...and a zobel at the output (10 Ohms- 100 nF )...
If the transistors (Q1,2,4 and 6) are all matched for gain, and the current sources are equal, the higher emitter current should not cause DC offset issues at all. Thermally couple them.
You might want another set of outputs for reliability. Prototype it and see how it behaves.
BC550C and BC560C is as low noise as you can get.
I always use C version, because they have highest gain.
Re: Question for all mighty ILIMZN and others...
Importantly, the gain increases as well, but you can trade tht for improved linearity by increasing the emitter resistors. There is, however, a compromise involved - with noise. This should not be a problem as you are designing a power amp so inputs signals are relativeli high and gain is not extreme.
The relationship between tail current and noise is not simple, there is usually a minimum, lower and higehr currents will increase it (but different mechanisms are involved). Input degeneration may also increase noise - however, as I said, in your case it should not be a problem - while the added linearity is a worthwhile goal.
Keep in mind ALL your stage currents are dictated to some extent by the LTP tail currents. This means that you want to make these thermally stable, at the moment they have a negative tempco, so as temperature increases, they decrease. Fortunately, in your amp this should not be a serious problem. Of course, R10 and R12 could have been a single resistor :)
You should also keep in mind that you cannot directly compare single and complementary diff inputs. as well as tail CCS topology and tail resistor topology. Increasing tail current for asymetric diff stages increases input bias current, which also increases DC offset. Wit symetric complementary diff. inputs the bias current is largely compensated, so higher tail currents can be used for equal DC offsets. There are other repercussions to do with differential input impedance of a LTP, which comes into play at HF - increased tail current decreases it.
Finally, there is the issue of power dissipation - typically an input transistor in a simple non-cascoded LTP has to span one whole supply rail across C-E, and this multiplies with the tail current/2.
You need gate protection zeners. Alternatively, although not immediately obvious, a reverse polarized diode from G to S of bothe MOSFETs will imit the gate voltage to the bias voltage plus 0.7V, but as this will typically be about 6-7V, the current limit will end up too high. Keep in mind you need to check Vgs versus Id plots for higher temperatures when choosing current limiting zeners!
Aparatusonitus mentions that these will not withstand 15mA, which is completely incorrect - since the C-E voltage is limited by the cascode arrangement, these can be run at quite high currents, and their gain exploited to the max. There are, however, concerns as to the design of a cascode driver, which I will address in a moment.
You could probably use BD140/139 (assuming C-E max voltage is within limits) without any great consequence to the performance here. What does count, is how well the chosen BJTs can dissipate power (as well as other SOA requirements).
With a cascode output stage, there are some points that need to be addressed:
1) Output impedance is very high, and voltage gain depends almost exclusively on the output impedance. This can present a problem as the output impedance, in your case, are the output MOSFETs. Although their input capacitance nonlinearities are somewhat compensated, for larger signals (as Vds becomes low), the nonlinearity directly impacts OL gain. Two approaches used to counter this are a) a buffer stage, and b) a stable shunt impedance to 'swamp out' the next stage nonlinear impedance effects (this, in your case, would be a resistor from driver Cs to ground). The first adds one stage and associated problems, the second reduces OL gain (not necesairly a problem). A combination can be used as one tends to partially cancel out the other.
2) You lose output swing, the output can only swing as far as Vrail minus cascode voltage. So, you want the cascode transistor base to be fairly close to the rail, keeping in mind the C-E voltage of the current gain BJT des to some extent impact it's gain. Since there tends to be rail droop as the power increases (i.e. output is required to swing closer to the rails), in many cases a 'halfwave rectifier' is added between the rail for the output MOSFETs and the driver side of the amp, in order to extend the maximum output swing. If properly constructed, this also filters out a lot of the halfwave-rectified-output-current artifacts created in the output stage, from being egenerated into the input stage via the rails.
3) Consider what happens when this amp clips. In theory, the full LTP tail lcurrent is available to drive the lower transistors in driver cascodes. Using the typical configuration and beta of these devices, we end up at cascode currents on the order of amperes, if the current is not limited. Fortunately, you have included Re's on the lower BJTs, so current is limited to 63mA, and maximum voltage between base and power rail is about 2.3V (LTP tail urrent times 330 ohms). The cascode voltage should not be lower than this, so there we have another compromise.
All in all, I think you have done very well! Just put the output MOSFETs on a very god heatsink and mount them properly for minimum thermal resistance - or, even better, you may consider powering the MOSFETs from a separate power supply with lower rail voltages.
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