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Old 9th February 2006, 06:15 PM   #31
lineup is offline lineup  Sweden
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I have used almost same circuit as in your discrete regulator.
Will work well.

You might need to add a compensation cap, to secure stability.
I should suggest you try 470pF or 1nF between Base and Collector of Q2.
Can be ceramic or small film capacitor.

The diode D1, should be other way.
Backwards, against current direction.

Maybe you should change to a lower value of R3 (3k3).
As for now Q2 is biased to only ~0.2 mA.
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Old 9th February 2006, 08:01 PM   #32
ilimzn is offline ilimzn  Croatia
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SInce you alredy have the transformers, the dice have been thrown

Be sure to include quite large filter caps for the auxiliary 45V supply as this is quite close to the 40V desired output. As the transformer is loaded, together with the output stage power supply, the auxiliary supply will droop as well. Adjust the regulator for a clean output under maximum amp load and minimum mains voltage, you may end up with less than 40V, but this is no big deal.

For a regulator, how about this simple tracking regulator I cobbled up, the schematic is from memory so there may be errors, beware! You may need to decrease the 1k resistors from C to B of the BD139/140 if the aux voltage droop is large, or they will run out of base current.
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Old 9th February 2006, 08:06 PM   #33
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Also, C4, 5, 11, 12 may not be needed (then the 4x4k7 zeber bias resistors can be consolidated into one or two resistors) as the caps in parallel to the zeners already provide a filter and 'bootstrap' current source. This is especially true since you intend on using regulated front end power rails.
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Old 10th February 2006, 12:13 AM   #34
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Quote:
Originally posted by ilimzn


Post #24
Ilimzin,

thanks to your exhaustive answer!
Actually I realize that my previous question was a bit pointless when it's so easy to just increase the capacitor level on the driverstage side.

Yes all is very well clear to me in your post, I agree with you on every point!

While reading through your post it reminds me again why I for a long time wanted to use a SMPS with PFC.

Cheers Michael
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Old 10th February 2006, 12:39 AM   #35
ilimzn is offline ilimzn  Croatia
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Quote:
Originally posted by Ultima Thule

While reading through your post it reminds me again why I for a long time wanted to use a SMPS with PFC.
Now, that's a project that is perhaps more complex than the amp it will be powering
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Old 10th February 2006, 09:21 AM   #36
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3.CAscode transistors (Q9,Q10) should have their own heatsinks so:
-would it be better to place them on separate heatsinks or not?
_cascode and css transistors have the same zener diode for a voltage reference, so should I thermaly couple zener diodes with css bjts(BC550/560) or
-I shoul thermaly couple zener diode and css bjt on the cascode`s bjt(BD139) heatsink ?
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Old 10th February 2006, 11:45 AM   #37
ilimzn is offline ilimzn  Croatia
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Quote:
Originally posted by bogdan_borko
3.CAscode transistors (Q9,Q10) should have their own heatsinks so:
-would it be better to place them on separate heatsinks or not?
_cascode and css transistors have the same zener diode for a voltage reference, so should I thermaly couple zener diodes with css bjts(BC550/560) or
-I shoul thermaly couple zener diode and css bjt on the cascode`s bjt(BD139) heatsink ?
Cascode transistor collector current is determined by the BC parts to within 1/hfe, so only the thermal dependence of their hfe will be acting here - the error would be a low single digit % worst case (and probably below 1% real life) so no problem there. hey do not need to be thermally coupled with anything, which means any adequate heatsink will do at your convenience. Short trace routing will probably put them close to the main heatsink so use that if you can.

Thermal dependence of cascode reference voltage does not alter the current through it in a signifficant manner. Again, it comes down to hfe variation with Vce of the BC parts, this is insignifficant in your case as Vce will only change in milivolts.

The thermal variation of the CCS current is another matter, as the cascode stage current also depends on this. Zener tempco breaks even at around 5-6V, below this it is negative, above it is positive. In your CCS the negative tempco of the zener reduces current and the negative tempco of the Vbe increases current, so to an extent you have cancelation. The negative tempco of the BCxxx BJT Vbe in the cascodes tends to increase the current in that stage, but this is reduced by the emitter degeneration there. It could be reduced some, if the oposing collector of your input LTPs (the one now conencted to the rail) was connected in a folded cascode fashion to the emitter of the BCxxx in the cascode, but this folded cascode conenction has it's own implications. In either case, I don't think this is problematic.

What you do want to do is thermally couple the LTP transistors (preferably all of them), or at least keep them very close to each other. This will insure minimum offset drift.

Either way I don't think you have a problem here that would necesitate special measures except for keeping the zener and CCS transistor relatively close to each other, and the two together, in such a place that the references for the + and - rail get heated up (by the proximity of the heatsink, for example) approximately equally - as the tracking of the LTPs is what cancels out your input bias currents and reduces offset.
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