Offset Correction using Bias Compensation

[lineup]

To correct Ouput DC offset
you can in any amplifier with differential inputs
provide bias current compensation at one or both input transistors.
( I do not mean servo - Only static currents )

This can be done using a constant current source feeding a transistor.
The base current of this transistor provide the bias current to compensate.

Attached application note is from an Onsemi datasheet.

My question is:
Shouldnt Q1 be a PNP transistor?

And how about Q3?
Looks crazy to me.

Can anyone show more ways to use currents to correct DC offsets.
Simple schematics, please!

[ilimzn]

Q1 should be NPN, otherwise the input of the OPamp will be clamped to -V through the forward biassed C-B junction.
Q3 E and C need to be reversed, though it may even work as is, just not very well (reverse beta of a BJT is generally very low).

[lineup]

Originally posted by ilimzn
Q1 should be NPN, otherwise the input of the OPamp will be clamped to -V through the forward biassed C-B junction.
Q3 E and C need to be reversed, though it may even work as is, just not very well (reverse beta of a BJT is generally very low).

In my mind Q1 should be a PNP
with the upper CCS feeding emitter
and the collector to -V
the tiny base current from Q1 base is conneted to the amp input.

If current source is 1 mA and hfe=500
it will give 2 uA bias current.


I did not know you can connect an NPN 'backwards' upsidedown
with E to positive and C to negative .....
and the base current will flow in opposite direction
from E to B
Is this a special case?

[Eva]

lineup is right, altough the concept of a "base follower" (a transistor connected to show 1/beta current gain) may seem hard to understand at first for some people. However, I think that this kind of correction requires insane degrees of transistor matching in order to be effective.

lineup:

Bipolar transistors are inherently reversible, you can exchange C and E in any device and it will still work as a transistor, but operating parameters will change dramatically. Particularly, beta will be much lower (usually less than 10) and the device will become somewhat slower and probably noisier (also Vce-max will become Veb-max and vice-versa). This happens because the junctions are not symmetrical at all. Small signal devices tend to behave better than power devices in these circumstances.

[lineup]

I used this bias current compensation in an amplifier once.
It worked good.

If the input pair is closely matched voltage B-E
you can come near to 0.000 Volt at both their bases.
While output is at 0 Volt.

If you look at my circuit with individual bias current adjustment to each input transistor,
you will see it looks like a symmetrical differential input stage.
But here PNP pair is used only for bias compensation.

[Bensen]

I will try to manage this as on the attached picture (link).

"V7" on the left would be the DC-servo. This one is connected throught a resistor to the midpoint of the complementary diff pair.
With this setup I can compensate offset's at the output to about +-1.4V.

picture:
http://www.diyaudio.com/forums/attac...amp=1136122736

thread:
Fully complementary FET-in FET-out design

The big advantage is that the currents in both legs of one diff pair always will be the same. --> both JFET's or BJT's will act the same.
With pot P1 I'll set the offset to 0Vdc when there is no input signal. P2 is there to set the bias currents.

What do you think about this?

Ben

[ilimzn]

Originally posted by lineup
In my mind Q1 should be a PNP
with the upper CCS feeding emitter
and the collector to -V
the tiny base current from Q1 base is conneted to the amp input.

That will work as well, just the compensation current reverses direction. To be honest I wasn't looking at the type of OPamp. 5534 has NPN inputs IIRC so needs positive (current flows into OP inputs) compensation current. Than means PNP is needed in the position of Q1, so on the schematic C and E need to be reversed.

[lineup]

Originally posted by lineup
I used this bias current compensation in an amplifier once.
It worked good.

If the input pair is closely matched voltage B-E
you can come near to 0.000 Volt at both their bases.
While output is at 0 Volt.

If you look at my circuit with individual bias current adjustment to each input transistor,
you will see it looks like a symmetrical differential input stage.
But here PNP pair is used only for bias compensation.

I did not get much reaction on my bias compensation circuit.
I find it a good option to
- be free to use whatver resistors in input, feedback
- keep these resistors almost current-free at idle, no signal input
- avoid DC-servo circuits
- keep correct current balance in input pair, = ideally equal currents

You do not have to use bias current addition to both legs of input differential pair.
Just using for the left, non-inverting is good enough to get zero DC-offset.

When using other methods, you can endup with input pair
does not have equal current and this is not a good thing
if I am to believe papers I have read by several good amplifier designers.
Thanks Bensen for pointing this out.
I have not had a look at your links.
But now I will.

[Bensen]

lineup,

I've been using the midpoint between the two diff pairs, because I don't have a CCS to feed the diff pair.
When you will use a CCS, you can control the current throught the diff pairs with the DC-servo.

See the attached picture to have an idea. I've found this somewere on this forum.

Greetz
Ben

[lineup]

Originally posted by Bensen
I will try to manage this as on the attached picture (link).

"V7" on the left would be the DC-servo. This one is connected throught a resistor to the midpoint of the complementary diff pair.
With this setup I can compensate offset's at the output to about +-1.4V.

picture:
http://www.diyaudio.com/forums/attac...amp=1136122736

thread:
Fully complementary FET-in FET-out design

The big advantage is that the currents in both legs of one diff pair always will be the same. --> both JFET's or BJT's will act the same.
With pot P1 I'll set the offset to 0Vdc when there is no input signal. P2 is there to set the bias currents.

What do you think about this?

Ben

I think this is a very good thing.
You have in your circuit two options to correct:
- DC-offset
- DC-servo

It think is not correct to call it 'DC-servo', because this term is used for a dynamic method which is:
Taking samples of output signal, filter it and
take difference between this and 0V and
feedback this to input
to correct for zero output offset.

I can not see you use DC-servo, but only static offset compensation.
And this is also a method I prefer, eventhough I do it another way.

One way uses no feedback correction
the other is an adjustment that corrects error from output using feedback.

DC-servo will work for all situations, with/without input Capacitor at amp input.
Other method, like input bias current compensation in my diagram,
will work alright with an input blocking Capacitor.