Current mirrors driving FETs

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Hello,

Please see the PDF schematic first (I know it's quality is not so hot!). Still trying to figure this out.

The late John linsley hood in one of his mosfet designs used a supertex FET namely the VN1210M as a VAS. Anyway, regarding the current mirror preceding it, he said he could bypass one of the resistors R5 with a capacitor, an option available because we are driving a high impedance load (the fet). Apparently this improves the dynamic transconductance of the mirror and so more gain.

JLH also choose low Vceo transistors in his mirror for more gain. The newer MPSA18 spring to mind nowadays!

My Question is, how much would a three transistor mirror (base compensated) improve Zout and DC closeness (matching) compared with a normal BJT mirror like in Doug Self's design. ? ( ps. I have forgot the name of the particular mirrror in question wilson/widlar etc)

JLH also says the FET improves negative PSRR also. I think this is a seperate issue to the mirror also. I personally would like to cascode the FET with a decent video transistors. Some of these BJTs are superb.

For the experts, would current mirror (D) work ?

If low Vceo transistors are used in the mirror (the base compensated one) - say MPSA18s. Can I use a higher Vceo transistor to compensate for it's base leakage ? (in a three terminal CCS driving a FET) and still use the capacitor to help out.

This might allow a cascoded JFET VAS stage for example, if the gain is enough.

Any techniques/advice welcome.

Kevin

PS. The Italian "Chianti" red wine is starting to seriously kick in! I can bearly type properly. This will be be my last post folks.

Have a good time with your wives tonight, I am :)
 

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Hi Kevin,

can't download your PDF for some reason but I'll comment.

You're best doing a sim and investigating aspects there - at least you can put relative figures on it.

Good luck with the Chianti and the wife (presume she's got a straw as well). I stick to the home brew beer these days - no surprises, no headaches. Wife likes it too - reckons it puts hair on her chest - probably mine.

Cheers,
Greg
 
Hello,

This might be a little better. I scanned in the .PDF and turned it into a poor jpeg. Wanna speak to JCX later, how he produces almost perfect schematics with LTspice for the forum. A former software engineer who worked at the company, done schematics with AutoCAD. Electronics World also do there schematics with AutoCAD sometimes. They look excellent!

Good luck with the Chianti and the wife (presume she's got a straw as well). I stick to the home brew beer these days - no surprises, no headaches. Wife likes it too - reckons it puts hair on her chest - probably mine.

LMAO!! :) :)

My uncle used to make his own beer also, well ale actually. Never tried any though, I was in america setting up a subsidiary industrial electronics company. More to it than meets the eye I can assure you....

Think I will go back to america and set up my own company. On the west coast though.

Regards

Kevin
 
Hopefully the JPEG works this time!
 

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A quicky regarding the current mirrors in the JPEG image above.

A. Is a typical bipolar CM with low Zout for driving BJT VAS's

B. Is a base compensated CM. I _think_ this is only suitable for FETs due to the higher Zout. Would appreciate answers on this?

C. Is taken from a JLH design in one of his MOSFET power amps. He bypasses one of the resistors to get more tranconductance. Because he is driving a fet. ie. high impedance load.

D. My proprosal (like Louis the 13th Cognac, if you have never had any before in Washington D.C., in theory ) is to do what JLH done with the cap bypass and add base compensation.

The transistors around nowadays are much better than 25 years ago.

The tricky part is matching the base current errors of high gain MPSA18's with a higher voltage device base compensator(essential) to ground.

Any advice/info welcome. I am an easy going bloke!

Kevin
 
What you are proposing is a wilson current mirror with an AC shunt for the DC degeneration. I don't see a reason why it would not work - can't see any new problems with it.
As far as the use of a Wilson CM per se, using high beta (>=100) BJTs usually reduces static imbalance to less than 1% in a simple two BJT CM, assuming at least 50mV degeneration in the emitters - usually this is more than good enough. Degeneration is done primairly for thermal drift compensation here, so JLH bypasses the resistor to increase gm back closer to it's non-degenerated value.
CM's are inherently high impedance, it is after all a current output device.
 
Thanks for your reply ilimzn.

There is only one slight problem bugging me and that is base leakage errors.

Say using MPSA18 (hfe=800, Vceo=45V) for the CM pair (main) and a higher Vceo device say a MPSA06 (hfe=150, Vceo=100) as a base compensator - which has to go to ground. The rails could be +/- 65V dc.

I am giving the stats on the MPSA06 only as an example of the problem. These are not accurate.

It's knowing what the base leakage is of the MPSA18 and trying other transistors to optimize this. (probably in good electronics books, but I am to lazy to do the math)

Best Regards

Kevin
 
A somewhat symmetric mirror+vas with low base current error:

mirror_fet_vas.gif


(note that gif and png are much better for line drawings than .jpg)

there are simpler approximations to an ideal diff pair but I think this works and has correct Vin scale factor

usual LtSpice source – just rename without .txt
 

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tiziano said:
I'm sorry is there anybody that can help me please ? I hope that my question is clear ( sorry for my English otherwise ) ...

Well, It is not as easy for me to see
what works with JFET,
as it is with plain, good old BC547 and BC557.

But I think your amplifier idea will work!

Make a low voltage test.
:att'n: Maybe use a dual regulated 12 volt supply ( +12V 0 -12V )
and start with a bit higher resistor values.
This will make lower current and not so much smoke
if anything goes wrong.


You do not need those 2 diodes in constant current source.
For a JFET CCS, Constant Current Source
we need only one JFET and
one Resistor (or Potentiometer for easy adjust CCS)

Your Circuit

And please!
Put some names, T1, T2, R1, R2 on those transistors and resistors in your circuit!
So we know what transistor/resistor we talk about ....
 
lineup said:


Well, It is not as easy for me to see
what works with JFET,
as it is with plain, good old BC547 and BC557.

But I think your amplifier idea will work!

Make a low voltage test.
:att'n: Maybe use a dual regulated 12 volt supply ( +12V 0 -12V )
and start with a bit higher resistor values.
This will make lower current and not so much smoke
if anything goes wrong.


You do not need those 2 diodes in constant current source.
For a JFET CCS, Constant Current Source
we need only one JFET and
one Resistor (or Potentiometer for easy adjust CCS)

Your Circuit

And please!
Put some names, T1, T2, R1, R2 on those transistors and resistors in your circuit!
So we know what transistor/resistor we talk about ....

I thank you very much, I'm sorry for the names ... I'll do surely next time ...

I have some other questions:

- Do you think that's an advantage to put FETs in place of BJTs on the Current Mirror and on the Constant Current Source ?

- On the CCS stage: if I put the resistor in place of the two diodes, I'll have not the inconvenients that I have normally with BJT when There is variation on the power supply and on the current absorbtion ?




Aftre that I have another question 'cause I'm gonna to build a pre for Piezo transducer ... I've found the diagarm that I show in the design in attachment ... the article tells that has a ain of about 50 ... ok I don't discuss .. but I'm interested to know in what manner works the FET Q1 ... is it like a current generator ? What is the advantage respect a normal resistor in this case ?

I thank you really very much
 

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- Do you think that's an advantage to put FETs in place of BJTs
on the Current Mirror
and on the Constant Current Source?


My personal Opinion:
-- Current mirror:
Normal BJT mirror better! Much better!

-- Current Source:
JFET makes very good current sources.
Keep current good, if power supply voltage change.
I think it is good advantage use JFET for this.

----------------------------------

- On the CCS stage:
if I put the resistor in place of the two diodes,
I'll have not the inconvenients that I have normally with BJT
when There is variation on the power supply and on the current absorbtion?


-- You are right. JFET current source is NOT much sensitive to Power supply.

-- You should replace those 2 diodes with wire ( = connect G, gate to V-)
See my attachment of a simple but good JFET Buffer.
Have a look at CCS. (the bottom JFET)

For JFET current source we only need this:
1 JFET
1 Resistor ... can use Trim-Potentiometer, for variable adjustamentione, for test circuit


--------------------------------

-- About that other circuit with BF245 JFET.
I do not know. Maybe somebody else will have comment ...

:) But I think of buying some BF245A and BF245B. :)
Very nice JFET and not difficult to find in my country.
They are perfect for making current sources in my pre-amplifiers!


lineup :cool:
 

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Great !

I thank you really very much ...

Practically I'll adopt the BJTs for the Wilson Current Mirror, and the FET for the CCS ... the only one thing is that the Power Suplpy is single and not dual ... it means that I have to generate a Vcc/2 in some manner ...

Really thank you ...

and if somone lese has some suggestion about the second circuit, it will be appreciated ... because is the first time that I see those configuration ...

Thank you again so much


Tiziano
 
yes.
I think is better using BJT small signal TO92 for mirror.

I have looked at many good hifi amplifiers using JFET and MOSFET.
But when these FET amplifiers will have one current mirror
I see only they use normal bipolar current mirror for this.

To make VC/2 for JFET is very easy,
because they take no bias current into Gate.

Use for example 2 resistors and one 10uF electrolyt.
2x22 kohm + 10uF will be very good.

-------------------

See attachment of SEWA 7 Watt power amplifier, with single supply.

R10 and R1, (10k + 4k7) divider set the voltage ( not VC/2 in this case )
C5 (220uF) makes filter against power supply disturbance.

R2 (100k) between R10/R1 is = input resistor = input impedance 100k
This resistor R2 is put to FET Gate to hold transistor at this voltage.

C2 (1uF) is the DC-blocking input capacitor.

R9 (100k) is added to charge C2 (from 0 volt to VC/2), if is nothing connected to input.

---------

If you in SEWA circuit make:
R10 = 10k (10-47k)
R1 = 10k (10-47k)
C5 = 10uF (10-100uF) electrolytic
.. and keep R2=100k and C2=1.0uF (1.0-4.7uF), and make R9 higher, 470k-1Mohm

...then
you will have a good input at VC/2 for a JFET input
with input impedance like ~80-90kohm


lineup
 

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Great, I thank you very much ...

Now a question: if I use MOS-FETs in place of FETs at the input stage ( the differential I mean ) to obtain very high impedance of input ( I have to use it with Piezo transducers ) do you think that will be possible without problem ? Or do you think thats is equal to use MOSFETs as well as FETs ?

I ask you that 'cause MOSFET has insulated gate by metal-oxyde layer, instead of FET has a normal NP or PN junction ... what do you think about ?
 
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