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Old 14th July 2005, 10:33 PM   #1
Jorge is offline Jorge  Brazil
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Default Comments on Intelectual creation, pls

Hello,

This is just a brainchild amplifier I've been doing latelly.
Maybe it won't ever be real, but anyhow I've always liked to toy with Electronics...

It's an OpAmp front end amp, using a super cascode and my pet triple output.
The compensation is not refined, it shows some peaks on heavy capacitive loads.

Notes:
There are 2 biasing diodes per base in the super cascode stage because I did not have a model for the green LED.
The BD139/140 pair was used just because I had the models (I know they will not stand the voltage).
The unusual 300nHy inductor in the output PNP emitter was the only way I've found to tame cross conduction. It may just be some limitation of the model.

Thanks for your comments,
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File Type: jpg opbip super cascode.jpg (33.1 KB, 537 views)
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Old 15th July 2005, 02:06 AM   #2
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Hi Jorge,

I think this needs a lot of work. The first stage of the discrete is not right! The 3K9 are way too high and should be more like 300R and that's a heavy load to drive from the chip. Also it's not good thermally as the biassing of this stage from CCS's tends to increase stage current at higher temperatures. Operating point stability is not good.

The cascode LED biassing and CFP drivers is as I used for the award winning Magnet amp (but with a comp diff FET cascode input stage).

Also the chip contributes only 20dB of gain at 20KHz where you need it most. Not the best compensation technique as it wastes GBW.

You asked.

Cheers,
Greg
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Old 15th July 2005, 02:56 AM   #3
Jorge is offline Jorge  Brazil
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Default Thanks, Greg

For your comments.

- I did not care for the opamp gain and loss in the CB stage very much because I already have about 40dB FB at 20K, crossing zero gain with 56 deg.
But from your words, it can be improved.

Can you elaborate on "the biassing of this stage from CCS's tends to increase stage current at higher temperatures"?

BTW, model CCIF IM (my favorite measurement) place all in band products at -100dB at 80V pp out..

A pity it's not real!

Regards,

Jorge
.
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Old 15th July 2005, 03:21 AM   #4
dimitri is offline dimitri  United States
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Default a lot of work

R4=R5=470 not 47, otherwise IcQ1=IcQ4, why use Sziklai pair at all?
omit C7
xchange D1,D4 (D2,D3) on 4.7V Zeners
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Old 15th July 2005, 03:25 AM   #5
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Hi Jorge,

I have attached a drawing for clarity. As temperature rises inside chassis the Vbe's drop and less current flows through the two R's. This current from the current sources is more and more deflected into the transistors Ic (to the next stage) as temp rises. Not really very good for overall thermal stability.

Cheers,
Greg
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File Type: png bad bias.png (896 Bytes, 341 views)
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Old 15th July 2005, 08:11 PM   #6
Jorge is offline Jorge  Brazil
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Default Re: a lot of work

Quote:
Originally posted by dimitri
R4=R5=470 not 47, otherwise IcQ1=IcQ4, why use Sziklai pair at all?
omit C7
xchange D1,D4 (D2,D3) on 4.7V Zeners
Dimitri

You're right about the 47 to 470 ohms change. Thanks for pointing it.

Re C7 - it helps (at least in simulation) to lower cross conduction of the outpt transistors (slow PNP).
LED for Zeners - not really necessary, the lower device of the cascode is happy with about 1V Vce, so an LED will do. I've used two reds because I don't have a model for a green one slightly more voltage).
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Old 15th July 2005, 09:04 PM   #7
Jorge is offline Jorge  Brazil
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Default Helo, Greg

Here it is again.

- The common base stage now has a more standard biasing. The current sources are there just to easy PSRR measurements.
- I've kept the common base since even as it was OL gain is 90dB, so...
- I changed the super cascode to a plain cascode. For some reason LTSpice didn't like the PNP side of it...weird results.
- I've redone compensation as well as I could, but it wasn't possible to avoid some around the opamp. Maybe the BW of the bipolar stages (even oly the cascode) is too narrow?
- I've applied a fair ammount of phase lead using the CB emitters.

Here's the new diagram
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File Type: jpg opbip cascode a cir.jpg (33.4 KB, 296 views)
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Old 15th July 2005, 09:06 PM   #8
Jorge is offline Jorge  Brazil
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Default Here's the freq response

.
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File Type: jpg opbip cascode a fr.jpg (48.6 KB, 265 views)
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Old 15th July 2005, 09:07 PM   #9
Jorge is offline Jorge  Brazil
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Default And here's the CCIR IM

Thanks for your time!

Jorge

Note; distortion 80V PP in 8 ohms.
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File Type: jpg opbip cascode a fft.jpg (42.0 KB, 265 views)
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Old 15th July 2005, 11:10 PM   #10
dimitri is offline dimitri  United States
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Quote:
Re C7 - it helps (at least in simulation) to lower cross conduction of the outpt transistors (slow PNP).
Yes, you are right, but think about the path of discharge current and about correspondent voltage drop on the other side. Would you like to discharge quickly, add two more transistors.

Quote:
LED for Zeners - not really necessary, the lower device of the cascode is happy with about 1V Vce, so an LED will do.
this is only simulation, in practice you need at least 3V across lower device, otherwise cascode distortion is much higher. Stick to soldering iron, not keyboard
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