The many faces of distortion
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andy_c
Banned

Join Date: Apr 2003
A while back in this thread, there was discussion about power amp output transistor models. I came up with a model for the MJL3281a that was a tweaked version of the OnSemi model, modified so its DC parameters were a much better fit to the data sheet characteristic curves than the standard one. I cloned this model to a PNP as well, making a symettric pair. I put these in the simulated circuit below, with a stepped DC current source as the load, going from -20 A to +20 A. This circuit has 0.22 Ohm emitter resistors, with the bias current adjusted to Self's optimum value for this configuration, 107 mA per device.

I plotted V vs I, which wasn't very interesting. But there's also the undocumented LTSpice d() plot function, which takes the derivative and plots it. This is more interesting, as it gives the output impedance at DC as a function of load current. In reality, this could be a multi-dimensional nonlinearity - that is, the output impedance could be a function of both output current and voltage, but I'll neglect that for now. Also, it would be more realistic to have a non-zero resistor from the junction of the two bias voltage sources to ground. A picture of the test simulation circuit is below.
Attached Images
 testcircuit.png (14.5 KB, 322 views)

andy_c
Banned

Join Date: Apr 2003
The output impedance vs current is shown in the graph below.

One interesting thing might be to try to duplicate this behavior as a nonlinear one-port using controlled sources that are polynomials. This might be done using MathCad or a similar tool to fit the I/V curve. Then, this nonlinear impedance could be put in series with an ideal, distortionless voltage source. Any computed distortion would then be due only to the impedance nonlinearity and its interaction with the load. The effects of feedback on this distortion could also be examined.
Attached Images
 outputimpedance.png (8.1 KB, 287 views)

 30th June 2005, 02:14 AM #193 Jorge   diyAudio Member   Join Date: Apr 2001 Location: Brazil Andy C Very interesting. And it holds for different Iq values? Thanks,
andy_c
Banned

Join Date: Apr 2003
Here it is with quiescent currents of 50 mA, 107 mA and 150 mA. Lowest impedance is highest current of course.
Attached Images
 outputimpedancestepped.png (8.7 KB, 287 views)

 30th June 2005, 02:54 AM #195 Jorge   diyAudio Member   Join Date: Apr 2001 Location: Brazil Looks like it's due to gm overlap of the output transistors in class AB. If so, very little can be done with classical topologies.
 30th June 2005, 03:05 AM #196 andy_c   Banned   Join Date: Apr 2003 It does seem to reinforce the concept of optimum bias though. Look at the ratio of max to min Z in the low-to-medium current region. The middle curve is clearly best.
 30th June 2005, 03:46 AM #197 amplifierguru Account Disabled   Join Date: Aug 2004 Location: Earth Hi Andy, Haven't you been having fun??? Want to do the same for a MOSFET (IRFP240/9240) output and different configs? Cheers, Greg
 30th June 2005, 04:04 AM #198 andy_c   Banned   Join Date: Apr 2003 Doesn't CircuitMaker do that? Seriously though, I could be talked into that if you're really interested in looking at it. There will be some asymmetry I'm sure, as well as some minor DC offsets.
 30th June 2005, 04:33 AM #199 amplifierguru Account Disabled   Join Date: Aug 2004 Location: Earth Well,er.. no it doesn't. Not last time I looked. Yes please. If it's no trouble? Greg
 30th June 2005, 04:39 AM #200 andy_c   Banned   Join Date: Apr 2003 Okay. What kind of configurations were you looking for? Variables might be: 1) Number of parallel output devices? 2) Source resistor value(s)? 3) Quiescent currents? 4) Others?

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